l4_linkResp_main_RateAdapter_Rate

Module Instance	Base Address	Register Address
`i_noc_ccu_ios_l4_linkResp_main_RateAdapter`	`0xFFD24C00`	`0xFFD24C08`

Size: 32

Offset: 0x8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`						`RATE` `RW 0x0`

l4_linkResp_main_RateAdapter_Rate Fields

Bit	Name	Description	Access	Reset
9:0	`RATE`	The ratio of outgoing to incoming throughput. This value determines what portion of a received packet will be stored before its head is transmitted. An optimal setting avoids transmitting bubbles, while adding no delay to packets. The ratio is expressed as 256 / (ratio - 1). For example, a 3:1 ratio of outgoing to incoming throughput would be indicated by value 0x06E. Note that throughput is the product of clock frequency x data bus width. A value of 0x000 causes the rate adapter to store a packet until either the entire packet is received or the buffer becomes full.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

9:0

RATE

The ratio of outgoing to incoming throughput. This value determines what portion of a received packet will be stored before its head is transmitted. An optimal setting avoids transmitting bubbles, while adding no delay to packets. The ratio is expressed as 256 / (ratio - 1). For example, a 3:1 ratio of outgoing to incoming throughput would be indicated by value 0x06E. Note that throughput is the product of clock frequency x data bus width. A value of 0x000 causes the rate adapter to store a packet until either the entire packet is received or the buffer becomes full.

RW

0x0