PCGCCTL
Power and Clock Gating Control Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_usbotg_0_DWC_otg_intreg | 0xFFB00000 | 0xFFB00E00 |
| i_usbotg_1_DWC_otg_intreg | 0xFFB40000 | 0xFFB40E00 |
Size: 32
Offset: 0xE00
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
Reserved |
L1Suspended RO 0x0 |
PhySleep RO 0x0 |
Reserved |
RstPdwnModule RW 0x0 |
Reserved |
StopPclk RW 0x0 |
|||||||||
PCGCCTL Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 7 | L1Suspended |
L1 Deep Sleep Indicates that the PHY is in deep sleep when in L1 state.
|
RO | 0x0 | ||||||
| 6 | PhySleep |
PHY In Sleep Indicates that the PHY is in Sleep State.
|
RO | 0x0 | ||||||
| 3 | RstPdwnModule |
Reset Power-Down Modules (RstPdwnModule) This bit is valid only in Partial Power-Down mode. The application sets this bit when the power is turned off. The application clears this bit after the power is turned on and the PHY clock is up.Note: The R/W of all core registers are possible only when this bit is set to 1b0.
|
RW | 0x0 | ||||||
| 0 | StopPclk |
Stop Pclk (StopPclk) The application sets this bit to stop the PHY clock (phy_clk) when the USB is suspended, the session is not valid, or the device is disconnected. The application clears this bit when the USB is resumed or a new session starts.
|
RW | 0x0 |