IC_SDA_HOLD 

         Name: I2C SDA Hold Time Length Register
Size: 24 bits
Address Offset: 0x7c
Read/Write Access: Read/Write
The bits [15:0] of this register are used to control the hold time of SDA during
transmit in both slave and master mode (after SCL goes from HIGH to LOW).
The bits [23:16] of this register are used to extend the SDA transition (if any) 
whenever SCL is HIGH in the receiver in either master or slave mode.
The values in this register are in units of ic_clk period.
This register controls the amount of time delay.
The relevant I2C requirement is thd:DAT as detailed in the I2C
Bus Specification.
Module Instance Base Address Register Address
sdm_i_i2c_0_DW_apb_i2c_addr_block1 0xFF8D0100 0xFF8D017C
sdm_i_i2c_1_DW_apb_i2c_addr_block1 0xFF8D0200 0xFF8D027C

Size: 32

Offset: 0x7C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_IC_SDA_HOLD

RO 0x0

IC_SDA_RX_HOLD

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IC_SDA_TX_HOLD

RW 0x1

IC_SDA_HOLD Fields

Bit Name Description Access Reset
31:24 RSVD_IC_SDA_HOLD 
Reserved bits - Read Only
 RO 0x0
23:16 IC_SDA_RX_HOLD 
Sets the required SDA hold time 
in units of ic_clk period, when DW_apb_i2c acts as a receiver.
Reset value: IC_DEFAULT_SDA_HOLD[23:16].
 RW 0x0
15:0 IC_SDA_TX_HOLD 
Sets the required SDA hold time 
in units of ic_clk period, when DW_apb_i2c acts as a transmitter.
Reset value: IC_DEFAULT_SDA_HOLD[15:0].
 RW 0x1