FIFOTH 

         
Name: FIFO Threshold Watermark Register
Size: 32 bits
Address Offset: 0x4C
Read/write access: write/read
Module Instance Base Address Register Address
i_sdmmc_sdmmc_block_1 0xFF8D1000 0xFF8D104C

Size: 32

Offset: 0x4C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

DW_DMA_Multiple_Transaction_Size

RW 0x0

RX_WMark

RW 0x3FF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

TX_WMark

RW 0x0

FIFOTH Fields

Bit Name Description Access Reset
30:28 DW_DMA_Multiple_Transaction_Size 
Burst size of multiple transaction; should be programmed same as
DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.
                                                 000  1 transfers
                                                 001  4
                                                 010  8
                                                 011  16
                                                 100  32
                                                 101  64
                                                 110  128
                                                 111  256
The units for transfers is the H_DATA_WIDTH parameter. A single transfer (dw_dma_single assertion in case of Non DW DMA interface) would be signalled based on this value.
Value should be sub-multiple of (RX_WMark + 1)* (F_DATA_WIDTH/H_DATA_WIDTH) and
(FIFO_DEPTH - TX_WMark)* (F_DATA_WIDTH/H_DATA_WIDTH)
For example, if FIFO_DEPTH = 16,
FDATA_WIDTH == H_DATA_WIDTH
Allowed combinations for MSize and TX_WMark are:
MSize = 1, TX_WMARK = 1-15
MSize = 4, TX_WMark = 8
MSize = 4, TX_WMark = 4
MSize = 4, TX_WMark = 12
MSize = 8, TX_WMark = 8
MSize = 8, TX_WMark = 4
Allowed combinations for MSize and RX_WMark are:
MSize = 1, RX_WMARK = 0-14
MSize = 4, RX_WMark = 3
MSize = 4, RX_WMark = 7
MSize = 4, RX_WMark = 11
MSize = 8, RX_WMark = 7
Recommended:
MSize = 8, TX_WMark = 8, RX_WMark = 7
Value Description
0x0 Burst of 1
0x1 Burst of 4
0x2 Burst of 8
0x3 Burst of 16
0x4 Burst of 32
0x5 Burst of 64
0x6 Burst of 128
0x7 Burst of 256
RW 0x0
27:16 RX_WMark 
FIFO threshold watermark level when receiving data to card.
When FIFO data count reaches greater than this number,DMA/FIFO request is raised. During end of packet, request is
generated regardless of threshold programming in order to complete any remaining data.
In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.
During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.
In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set.
12 bits-1 bit less than FIFO-count of status register, which is 13 bits.
Limitation: RX_WMark <= FIFO_DEPTH-2
Recommended: (FIFO_DEPTH/2) - 1; (means greater than (FIFO_DEPTH/2) - 1)
NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at the end of packet, even if remaining bytes are less than threshold. In this case, there will be some data left in the FIFO. It is the responsibility of the application to reset the FIFO after the CCS timeout.
 RW 0x3FF
11:0 TX_WMark 
FIFO threshold watermark level when transmitting data to card.
When FIFO data count is less than or equal to this number,DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated,regardless of threshold programming.
In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty).
In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred.
12 bits-1 bit less than FIFO-count of status register, which is 13 bits.
Limitation: TX_WMark >= 1;
Recommended: FIFO_DEPTH/2; (means less than or equal to FIFO_DEPTH/2)
 RW 0x0