reg_caltiming3 

         Calibration Timing 3 Register
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF8010088

Size: 32

Offset: 0x88

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_wr_to_pch

RW 0x0

cfg_t_param_wr_to_rd_diff_bg

RW 0x0

cfg_t_param_wr_to_rd_diff_chip

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_wr_to_rd_diff_chip

RW 0x0

cfg_t_param_wr_to_rd

RW 0x0

cfg_t_param_wr_to_wr_diff_bg

RW 0x0

reg_caltiming3 Fields

Bit Name Description Access Reset
29:24 cfg_t_param_wr_to_pch 
iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_pch[5:0]
Name:Wr to Precharge
Description:Write to precharge command timing.
RW 0x0
23:18 cfg_t_param_wr_to_rd_diff_bg 
iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_rd_diff_bg[5:0]
Name:Wr to Rd Diff bank Group
Description:Write to read command timing on different bank groups, DDR4 only.
RW 0x0
17:12 cfg_t_param_wr_to_rd_diff_chip 
iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_rd_diff_chip[5:0]
Name:Wr to Rd Diff Chip
Description:Write to read command timing on different chips.
RW 0x0
11:6 cfg_t_param_wr_to_rd 
iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_rd[5:0]
Name:Wr to Rd Same Bank
Description:Write to read command timing.
RW 0x0
5:0 cfg_t_param_wr_to_wr_diff_bg 
iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_wr_diff_bg[5:0]
Name:Wr to Wr Diff Bank Group
Description:Write to write command timing on different bank groups, DDR4 only.
RW 0x0