HCINTMSK2 

         Host Channel 2 Interrupt Mask Register
Module Instance Base Address Register Address
i_usbotg_0_DWC_otg_intreg 0xFFB00000 0xFFB0054C
i_usbotg_1_DWC_otg_intreg 0xFFB40000 0xFFB4054C

Size: 32

Offset: 0x54C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

RO 0x0

FRM_LST_ROLLIntrMsk

RW 0x0

RESERVED1

RO 0x0

BNAIntrMsk

RW 0x0

DataTglErrMsk

RW 0x0

FrmOvrunMsk

RW 0x0

BblErrMsk

RW 0x0

XactErrMsk

RW 0x0

NyetMsk

RW 0x0

AckMsk

RW 0x0

NakMsk

RW 0x0

StallMsk

RW 0x0

AHBErrMsk

RW 0x0

ChHltdMsk

RW 0x0

XferComplMsk

RW 0x0

HCINTMSK2 Fields

Bit Name Description Access Reset
31:14 RESERVED 
RESERVED
 RO 0x0
13 FRM_LST_ROLLIntrMsk 
Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
This bit is valid only when Scatter/Gather DMA mode is enabled.
Value Description
0x0 Descriptor Rollover Interrupt Mask
0x1 Descriptor Rollover Interrupt not masked
RW 0x0
12 RESERVED1 
RESERVED
 RO 0x0
11 BNAIntrMsk 
BNA  (Buffer  Not  Available)  Interrupt  mask  register  (BNAIntrMsk) 
This bit is valid only when Scatter/Gather DMA mode is enabled.
Value Description
0x0 BNA Interrupt Masked
0x1 BNA Interrupt not masked
RW 0x0
10 DataTglErrMsk 
Data Toggle Error Mask (DataTglErrMsk)
In  scatter/gather  DMA  mode  for  host, 
interrupts will not be generated due to the corresponding bits set in 
HCINTn.
Value Description
0x0 Mask Data Toggle Error
0x1 No Data Toggle Error Mask
RW 0x0
9 FrmOvrunMsk 
Frame Overrun Mask (FrmOvrunMsk)
In  scatter/gather  DMA  mode  for  host, 
interrupts will not be generated due to the corresponding bits set in 
HCINTn.
Value Description
0x0 Mask Overrun Mask
0x1 No Frame Overrun Mask
RW 0x0
8 BblErrMsk 
Babble Error Mask (BblErrMsk)
In  scatter/gather  DMA  mode  for  host, 
interrupts will not be generated due to the corresponding bits set in 
HCINTn.
Value Description
0x0 Mask Babble Error
0x1 No Babble Error Mask
RW 0x0
7 XactErrMsk 
Transaction Error Mask (XactErrMsk)
In  scatter/gather  DMA  mode  for  host, 
interrupts will not be generated due to the corresponding bits set in 
HCINTn.
Value Description
0x0 Mask Transaction Error
0x1 No Transaction Error Mask
RW 0x0
6 NyetMsk 
NYET Response Received Interrupt Mask (NyetMsk)
In  scatter/gather  DMA  mode  for  host, 
interrupts will not be generated due to the corresponding bits set in 
HCINTn.
Value Description
0x0 Mask NYET Response Received Interrupt
0x1 No NYET Response Received Interrupt Mask
RW 0x0
5 AckMsk 
ACK Response Received/Transmitted Interrupt Mask (AckMsk)
In  scatter/gather  DMA  mode  for  host, 
interrupts will not be generated due to the corresponding bits set in 
HCINTn.
Value Description
0x0 Mask ACK Response Received/Transmitted Interrupt
0x1 No ACK Response Received/Transmitted Interrupt Mask
RW 0x0
4 NakMsk 
NAK Response Received Interrupt Mask (NakMsk)
In  scatter/gather  DMA  mode  for  host, 
interrupts will not be generated due to the corresponding bits set in 
HCINTn.
Value Description
0x0 Mask NAK Response Received Interrupt
0x1 No NAK Response Received Interrupt Mask
RW 0x0
3 StallMsk 
STALL Response Received Interrupt Mask (StallMsk)
In  scatter/gather  DMA  mode  for  host, 
interrupts will not be generated due to the corresponding bits set in 
HCINTn.
Value Description
0x0 Mask STALL Response Received Interrupt
0x1 No STALL Response Received Interrupt Mask
RW 0x0
2 AHBErrMsk 
AHB Error Mask (AHBErrMsk)
In  scatter/gather  DMA  mode  for  host, 
interrupts will not be generated due to the corresponding bits set in 
HCINTn.
Value Description
0x0 AHB Error Mask
0x1 No AHB Error Mask
RW 0x0
1 ChHltdMsk 
Channel Halted Mask (ChHltdMsk)
Value Description
0x0 Channel Halted Mask
0x1 No Channel Halted Mask
RW 0x0
0 XferComplMsk 
Transfer Completed Mask (XferComplMsk)
Value Description
0x0 Transfer Completed Mask
0x1 No Transfer Completed Mask
RW 0x0