SMMU_CB1_PMCNTENCLR

         Provides the equivalent of the PMCNTENCLRx register, in the register map of a translation context bank. Disables any implemented event counter.

Note: For register and programming information, please refer to the ARM CoreLink MMU System Memory Management Unit Technical Reference Manual.

Module Instance	Base Address	Register Address
`i_aps_smmu_secure_registers`	`0xFA000000`	`0xFA021F44`

Size: 32

Offset: 0x21F44

Access: WO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`												`P3` `WO 0x0`	`P2` `WO 0x0`	`P1` `WO 0x0`	`P0` `WO 0x0`