By the end of the presentation, you will be able to construct complete models using VHDL. You will be able to generate general logic functions and build hierarchical designs.

We will begin the course with an overview of VHDL . Next we will discuss design units within the language. This section includes discussion of entities, architectures, configurations, and finally packages.

We will then look at the language in more detail, studying the constructs used within the language to create models. These include constants, signals, processes.
Next we will learn how VHDL code is synthesized and look at to construct some commonly used functions.

Finally we will discuss designing hierarchically with in VHDL.

VHDL stands for VHSIC Hardware Description Language. VHSIC stands for very High Speed Integrated Circuit.

VHDL is an IEEE standard hardware description language. It is used for both simulation and Synthesis.

In 1980 the U.S. department of defense started a program that eventually produced VHDL. The language was ratified as IEEE standard 1076 in 1987. In 1993 the IEEE VHDL standard was revised.

There are a few terms that we will be using throughout this course.
HDL stands for hardware description language.
Behavior Modeling describes a component by its input/output response. This is also sometimes referred to as black boxing.
Structural Modeling describes a component in terms of its lower level components and primitives.

Register Transfer Level, often referred to as RTL, is a type of behavior modeling that is synthesizable.
Synthesis is the process by which HDL code is translated into a circuit. After the code is translated the circuit is optimized. The precise method of optimization depends on the synthesis tool and options that you set with in that tool.
A process is the basic unit of execution in VHDL. Within a process, statements execute sequentially, however processes themselves execute concurrently.

Behavior modeling specifies only the functionality of a circuit, but does not indicate the actual structure of the circuit. The relationship between a components inputs and outputs is clearly defined, but only at a high level. The actual circuit implementation is left up to the interpretation of the compiler.

Structural modeling, like behavior modeling specifies the functionality of a circuit, but it goes further and calls out a specific hardware implementation, including building blocks and their connections.

During RTL synthesis, code that is written is analyzed and equivalent logical structure is generated. So in the upper left, you can see a process block with a case statement inside. When coding this case statement, the logic I am seeking is a 4-input mux. The synthesis tool, recognizing the case statement structure, performs
perform2 steps, translation and optimization. During translation, the synthesis tool directly translates the HDL code in a gate implementation. During optimization, the synthesis tools improves the logic, by making it smaller or faster. It may make the logic smaller by removing redundant logic or make it faster by adding some parallel structures in it.

Both VHDL and Verilog can be used as higher level languages support behavioral synthesis.

Other languages like ABEL, PALASM and AHDL are more structural. With those languages, I specifically instantiate the component I want in my design, such as a d-flip flop and the tool goes into a library and drops that into my design. Very similar to low level schematic entry of the old days.

VHDL supports both methods of designing, both by inference and by instantiation which is what makes it so powerful. By simply describing the functionality of a circuit and letting the synthesis tool build it for me, you can produce very powerful functions in just a few lines of code. Doing this using a structural language is much more like programming in low level assembly with the circuit having a very specific implementation, so changes to that implementation do not scale easily and require much more effort.

This slide shows the flow diagrams followed by VHDL synthesis and simulation tools. Notice the tools use distinctly different flows. On the right, you can see that the simulation compiler takes your VHDL design and any VHDL libraries used to creates a simulator-specific simulation model. It then executes simulation on this model. Using this model allows a simulator to perform faster simulations than if it was trying to read the code line-by-line while a simulation is actually running. During simulation, the tool takes any test vectors or stimulus provided and by you and produces output waveforms or text files that you can use to verify proper operation. As an alternative, you can also write your simulation stimulus using generic VHDL code, called a testbench. The testbench codes gets compiled along with the design, so that the stimulus is also in the compiled simulation model. This means you do not need to provide simulator-specific test vectors when you execute your simulation. The advantage of the testbench is that your stimulus is portable just like the design files. Notice in this flow there was not mention of hardware or target architecture. This is because a simulator is going to execute code as it is written. In a sense, it really does not care where the design is going as it is only concerned about interpreting the functional description provided by your VHDL code.

On the left, the synthesis compiler takes the same VHDL design and libraries to produce a synthesized netlist. This netlist is your design translated into the primitives that make up the target hardware architecture. Notice that in the synthesis flow a technology library was used. Every FPGA family has a different library that a synthesis tool uses to map a design to its specific architecture. Using the generated synthesized netlist, the design can be placed and routed in the actual target device. If post synthsis simulation is desired, the synthesis tool can produce a VHDL output file that represents the synthesized results. This can be taken back to the simulation tool and re-simulated. This provides a check to ensure that the synthesis did not produce any errors.

Here are some more VHDL basics. The language consists of synthesis and simulation constructions. Some constructs are used for simulation only, while others can be used for both. VHDL is make up of reserved keywords, like most text languages, and is NOT case sensitive. Every VHDL statement MUST be terminated by a semicolon with spaces used for readability and are ignored. Comments can be added to the end of the line with a double dash preceding it or a comment block may be added to provide more verbose information by preceding the comments with an backslash and asterisk and ending them with an asterisk and backslash, similar to C.

We will use the following four types of design units throughout this presentation. First we will talk about entities.
An entity defines the external view of your design. All designs are expressed in terms of entities. The top-level is always an entity. If you are designing hierarchically, there will be lower level entities. An entity can be thought of as similar to a symbol. It defines port information

An architecture defines the functionality of an entity. It is used to fill in the details of a model. Every design that you can simulate has an architecture.

A configuration associates an entity and an architecture. Using configurations, you can have more than one architecture per entity. This allows you to create one entity, but have it function in different ways.

A package is a collection of commonly used code. It can be referenced by other parts of your design. A package can be thought of as a toolbox or a library that contains information needed by the rest of your design.

All designs are created from entities.
Here is the basic structure for an entity declaration. The keyword entity begins the entity statement. The name of the entity follows the keyword. The line ends with the keyword IS.
An entity consists of two sections, the generic declarations and the port declarations. Generic declarations are used to pass information into the model. The port declarations section describes the inputs and outputs to the entity.
There are several ways to close the entity depending on what your preference is and what version of VHDL you are trying to support.

The port declaration is used to declare the I/O to your entity and occurs within the entity declaration after the generic declaration. Similar to the generic declaration, the port declaration starts with the keyword port and then, within parenthesis, list all the of the I/O. It ends with a a semicolon.

The structure for a port declaration goes, class, object name: mode and type. The class is most always signal, though it doesn’t have to be, so you almost never see the word signal appear. The object name is the name of the I/O port. In this example, the object names are clk, clr and q. Since clk and clr are of the same type, they are declared together, separated by a comma.

The mode is the direction of the port. In VHDL, the keywords for directions are in for input, out for output, inout for a bidirectional and buffer for an output with internal feedback. Typically input signals and only be read from not written to. Outputs can only be written to, not read from. Inouts must be used as inputs and outputs. With buffers, physically in the design you will have an output pin, but you will be allowed to read from it as well. Use care when using buffers as there are restrictions on them when connecting them to other design blocks hierarchically. Personally, I typically stick with in, out and inout.

And lastly, the type is the data type defines the type of values that can be held by your I/O.
Like the generic declaration, the semicolon is used as a separator and the last port declared is not followed by a semicolon.l

Generics are values that can be passed into an entity at compilation time. We use them to make our entities parameterizable when designing hierarchically.

The generic declaration is contained inside of the entity declaration. We use the keyword generic and within parenthesis list the generics.

The format for a generic declaration goes class, object name type and initial value. The class signifies what can be done to the generic. Generics are almost always constants and the keyword constant is usually left out. The object name is the name of the generic that will be used within your model. The type is the data type, which specifies the values that your generic can hold. Finally, the initial value is optional.

As you can see in the example, the generic declaration itself is considered a statement and ends with a semicolon. Within the parenthesis, the generics are listed with semicolons separating each one. Since the semicolon is used to separate the list, there is no semicolon after the last generic, as you can see after the word up. Also notice you can declare multiple generics in one line if they are of the same time and initial value, by using the comma. Thus tplh and tphl are both generics of type time initialized to 5 ns. And tphz and tplz are both generics of time initialized to 3 ns.

The architecture describes the internal logic to your model, analogous to a design schematic. While the outside world can see the entity name, the parameters being passed to it and the port connections, it cannot see the actual guts of the block. We use the architecture to describe the functionality and possibly the timing of the model.

Architectures must be associated with an entity, but an entity can have multiple architectures associated with it. This is done sometimes in simulation when a designer wants to use two different sets of test vectors to test the design. He or she may have two architectures and will select one at compile time. Multiple architectures may also be used by designers when they have one architecture that contains a a synthesizable model and another architecture that contains a simulatable model. Depending on what action they are performing, be it in synthesis or simulation, they will select the appropriate architecture.

Within an architecture are implied and explicit processes that execute concurrently. We’ll be discussing processes in a bit.

When coding an architecture, there are two methods that can be used.
Behavioral: with the design described with an RTL and functional coding style,
Structural: which interconnects gates and components together like a netlist,
or a mixture of both.

Similar to the ENTITY block, the architecture can be terminated with several different methods depending on which version of VHDL you are supporting.

The architecture starts with the keyword architecture. Following that is the name of the architecture. You can use any alphanumeric name for your architecture. In fact, many designers will re-use the same name for all of their architectures. Since architectures are invisible to the outside world, reusing the same name is not an issue. If you have multiple architectures for the same entity, then the names must be unique.

After the architecture name, you have the the keyword OF and then the name of the entity that this archiecture belongs to, followed by IS.
Then yo have the architecture declaration section. Local identifier that you use insde the architecture that are not ports or generics must be declared in the architecture declaration section before that can be used. In this example, that could be a signal, a constant or an enumerated data type. All of these we will take more about later.

After the declaration section, you have the keyword BEGIN followed by the architecture body. The arch body contains the executable lines of code within your design, made up of various processes.

End your architecture with the line end architecture and then the architecture name.

The 3rd design unit, the configuration, is used to associate an entity to an arch. Since entities can have more than one architecture associated with them, the configuration assigns a unique name to a single entity architecture pairing. Then instead of having to choose a pair, you simply select the configuration name and the tool understands which entity arch pair you are referring to. While they are supported in synthesis environments, they are used more so in simulation environments where again I may have multiple sets of test vectors applied to the same entity.

The format for a configuration starts with the keyword configuration. Then the configuration name followed by OF the entity name IS FOR the architecture named and END FOR.

End your configuration with the keywords END configuration and the configuration name.

Here you can see an entity, an architecture, and a configuration all working together.
The entity defines the ports.
In this example a, b, and sel are inputs, x, y, and z are outputs.
The architecture defines three muxes.
You can see that the three muxes are coded using three different styles, a simple signal assignment, a conditional signal assignment, and a selected signal assignment. We will look at these assignments in detail later in the presentation.
Finally the configuration ties the architecture and the entity together. Once again configurations are typically used in a simulation environment.

Packages are a way to store reusable code throughout a model. Instead of declaring the same construct to use in each separate VHDL file, I can place the information in a package, source the package and save myself some typing.

The package consists of a package declaration and a package body. The package declaration is required and is used to declare identifiers that you will be using, such as type declarations and subprogram declarations. The package body is an optional section. Though you can declare items in the body, it is typically use to define the functionality of the subprograms that were declared in the package declaration section.

VHDL has 2 built-in packages called the standard and textio packages. The standard package defines built-in VHDL data types that can be used for designing and associated operations that go along with them. The textio package provides support for file operations, for example reading and writing to external data files.

Here we have an example package. You can see its two major functional blocks, the PACKAGE section and the PACKAGE BODY section. The package section contains constant declarations, port information, and a function declaration.

The PACKAGE BODY section contains the function itself. You can see that this example implements a basic compare function.

Libraries contain a package or collections of packages. They are essentially directories where your packages are located. Using a library, I can assign a unique name to a directory where my packages are compiled. Then by source the library name, the tool knows where to go look for the packages my design calls out.

Libaries can come from various places. VHDL has a standard library that contains the standard packages I referred to in the last slide. IEEE came along and created additional libaries that are supported by almost all VHDL compilers. Specific silicon vendors like Altera created further libraries from which you can call vendor-specific information. And you can also create your own libraries, in which you store your own units for reuse.

The current project library in which you are design is called the working library. If you don’t indicate that you want something compiled into a specific library, then it will automatically be compiled in your working library or directory.

Before you can use any package, it must be compiled into a library. If you don’t compile it into a particular library name, then it will automatically be compiled into the working library name WORK.

To use a package, you must first call out its library using the library clause. Again, the library name is a symbolic name that refers to a directory containing your compiled packages. Each VHDL compiler you use will have a specified way to associate a name to a particular directory path.

To call out a library, You type the keyword library followed by the library name. After that, you use the USE clause to call out the package within the library.

Both the library WORK and standard STD are considered implicit libraries and do not need to be explicitly called out.

Here is an example of the library and use clauses. In this example, I am calling out the IEEE library, since it is not an implicity library. If I had multiple libraries that I wanted to use, I could list them separated by commas.

For the use clause, I type the library name (dot) the package name (dot) the object in the package I want to reference. If I want the entire package available to the model, then I can use the keyword ALL, which you will find most designers do since it is easier and memory impact on your system is neglibile.

The libray and use clauses are placed at the very beginning of your model so that they can be accessed by all of the design units in your model.

We mentioned that the library std is included automatically. This library contains the standard package. The standard package includes built in data types and the operators needed to support the built in data types. You can see that the data types included in the standard package are bit, Boolean, integer, real, and time. This library also contains the textio package. This package provides file operators.

The type bit, included in the standard package, can take on the value of either ‘0’ or ‘1’.

The BIT_VECTOR type is an array of bits. Here you can see examples of defining both a bit and a bit_vector.

The BOOLEAN type simply takes on the values true and false, while the integer value can store up to a 32 bit number. You can use both positive and negative numbers with the integer type.

In order to model hardware even better, IEE developed additional packages that can be used. These are defined in the IEEE library. The packages are std_logic_1164 which defines a brand new data type called std_logc and functions to go along with it. Originally, other vendors developed additional packages, such as std_logic_signed, which extended the capabilities of the std_logic data type, such as allowing designers to use std_logic in arithmetic calculations and converting from and to std_logic from other data types. Since then, IEEE has released the numeric_std which has replaced those other vendor-specific packages. This new packages defines the unsigned and signed data types and operations that can be performed with them. The older vendor-specific packages have since been deprecated.

The std_logic type can take on nine different values. This makes it a more flexible data type than ‘bit,’ which can only take on two values. This data type does support signals with multiple drives.

The std_ulogic is similar to the std_logic type, but it does not support multiple signal drives. If a std_ulogic signal has multiple signal drives, an error will be generated.

Before we go on to architecture modeling, let’s review the main points we have covered thus far.

First we talked about some basic terminology. Synthesis, the step in which HDL code is translated to a circuit, is a very important concept. Behavior modeling allows you to specify the functionality of a circuit, while structural modeling allows you to specify both the functionality of the circuit and its implementation.

Next we covered the basic design units in VHDL. Remember that an entity is similar to a symbol and an architecture is similar to a schematic. A configuration associates an entity with an architecture.

Then we looked at packages. A package allow you to reuse code throughout a model.

Finally we talked about libraries. A library contains one or more compiled packages. The work library is automatically created and contains your current model. The ieee library contains a number of useful packages, such as std_logic_1164.

Constants are used to assign a value to a name. They are used to make code more readable and add flexibility. By using constants, I can change bus widths or enable/disable design features, just by changing one value.

Generics are essentially constants whose values can be passed in from other modules and changed at compile time. Local constants, invisible outside the model are declared in the arch declaration. To declare a constant, you use the keyword constant followed by a identifier name, the data type := and the value you are assigning to the constant. The value must be valid for the constant’s data type. So in this example you can see the identifier bus_width is being assigned an integer value of 16.

Constants cannot be changed during design execution.

A signal in VHDL represents a physical interconnect. You can see that in this example, signals feed the first process on the left, which could represent something like a MUX. The output of this block is fed to the process on the right, using another signal. Finally yet another signal carries the output from the process on the right.

When declaring a signal, you specifiy SIGNAL, give it a name and then the type of signal such as a STD_LOGIC or in this case a STD_LOGIC VECTOR which is used to define a bus. In this example we are defining an 8 bit bus from 7 down to 0, with 7 being the MSB and 0 being the LSB.

There are a few different ways to assign values to a signal. In this example, temp is an eight bit signal. You can see its declaration at the top of the slide. Signal assignments are defined with the less than equal to symbol as shown in these examples.

The first example shows all eight bits being assigned at once. In this case we are assigning the signal with a binary value, which is the default and since we are defining multiple bits at the same time, they are separated by quotes. In the second example a hex value is being assigned to the signal temp.

The next case is known as “Single bit.” In this example a 1 is being assigned to bit seven of the signal temp. For single bit assignments, single quotes are used.

VHDL 2008 allows for enhanced bit literal assignments that were previously restricted to multiples of 4 for hex values and multiples of 3 for octal values.

Now, it is possible to assign explicit widths that are either sign or unsigned and can even contain meta values, such as undefined or high impedance as shown in these examples

In the first example, we are assigning a 6 bit hex value for temp that is a 0F, which means the 0 only represents 2 of the 4, 0’s we would have had previously.

In another example, we can see that we are assigning a 6 bit signed value of F to the signal. Since F is a 1111, it automatically sign extends the 1 to fill the full 6 bit field. We can also see that when we specify an Octal 7 to the 6 bit signal, the upper bits are filled with 0s automatically.

It is important to note that we are using double quotes for all of these assignments and they are not case sensitive either.

Here is an example of a signal being used as an interconnect.

When assigning signals to expressions, we use the format signal name gets the value of an expression, just as we saw before for assigning values.

So in the example we show here we see that we are assigning the signal qa to get the output of r OR’d with t. This is also how we define a signal that is used as an interconnect between logical blocks. And qb will get the output of qa and the inverted output of g XOR’d with h. These signal assignments have the function of implying the logic shown in the diagram above.

The next type of assignment that we will talk about is known as a conditional assignment. A conditional assignment acts like a if else statement. In this example, if sela=’1’ than q gets a. If sela does not equal ‘1’ than we take the else and check to see if selb=’1’. If selb = ‘1’ than q=’b.’ If neither of these statements is true than q=’c.’

You can see that this code synthesizes to two MUXes. If sela=’1’ q becomes ‘a’ regardless of the selb signal.

The final type of assignment is known as a selected signal assignment. A selected assignment acts like a case statement. All possible conditions are considered at once. You can see that a selected signal assignment translates into one MUX with as many inputs as there are conditions. The ‘when others’ clause covers all cases not specifically already covered.

In the VHDL built-in libraries, certain operators can only be used with certain data types. Or example, arithmetic operators can only be used with data type integer and boolean operators can only be used with type bit. What about other data types like std logic? Well ot do this, we have to use operatore overloading.

Operator overloading allows the same operator to be used with multiple data types. This done by declaring a function whose namem is the same name as the operator itself. This is done by enclosing the character in double quotes. To make this easier, IEEE-defined data types have already been overloaded for us to to use the same operators as standard data types in VHDL.

The signal assignments we have talked about so far have been implied processes that are executed anytime one of the expressions on the right hand side changes. But, we can define a process explicitly as well.

The format to do this is to provide an optional, but suggested, descriptive label for the process followed by the keyword PROCESS and then an optional sensitivity list. The sensitivity list is optional because it is only really needed for simulation. Since the code we are writing is synthesized into actual pieces of hardware, it will operate exactly as the implied process works, when an input to the process changes it will cause the output signals to be updated. If we do not specify the sensitivity list we will have simulation mismatches, so it is strongly suggested. To make your life easier, in VHDL 2008 we have the option of using the keyword all to represent all of the input signals rather than specifying them individually.

After the process declaration is a local objects section that allows the definition of constants, custom types and variables. The actual functional contents of the process is defined between a begin and end process set of statements.

Here are two example of explicit processes. The first process is assigned the label proc1 and it is sensitive to a and b. Thus, if a or b changes, this process turns on and executes the sequential statements inside. Once it is done executing those statements, it will wait for another transition on a or b to execute the process again.

In the second example, process2, this example does not have a sensitivity list, so this process begins executing immediately at the start of simulation. Again, the statements inside are executed sequentially. This time when the process reaches the end, a wait on statement is seen. This wait on statement forces the process the process to wait until a or b transition before the process loops around and begins executing again.

While the behavior of two processes may seem different, they are actually identical. This is because all processes begin executing at the start of simulation in order to define the initial output values. Thus, it’s during the second iteration of process1 when the sensitivity list starts controlling its execution. Thus, as I mentioned in the previous slide, having a sensitivity list is said to “imply” having a wait on statement at the end of the process since their behavior is the same.

Having a sensitivity list and wait statements inside the same process is not legal in VHDL.

If-Then statements act similarly to conditional signal assignments. You can see that like a conditional assignment statement, a if-then statement is translated to a MUX. When using if-then-else, the statements are translated to a string of muxes.

Case statements act similarly to conditional assignment statements. All cases in a case statement are considered at once. While if statements synthesize to a string of two input MUXes, case statements synthesize to one MUX with many inputs.
We have talked about how to make signal assignments and how to control the flow of your code using if-then and case statements. Next we will look at loops in VHDL.

There are three basic loops that we will talk about, Infinite Loops, While Loops, and For Loops. Inside each of the loops are sequential statements. When the end of the loop is reached, control is transferred back to the beginning of the loop. This process continues until an exit condition for the loop is met.

An infinite loop does not exit until an EXIT command is reached. The EXIT command can be embedded in an If statement so that the loop is only exited if some condition that is evaluated by the If statement is true.

A While loop exits when some condition defined at the start of the loop evaluates to false.

A for loop executes some specified number of times. In some programming languages the identifier can be modified with in the loop, but VHDL does not allow this.

This example of RTL code shows a case statement. We will learn more about case statements later, but you can see that a case statement is typically translated to a multiplexer. The first step during synthesis, directly translating the HDL code, results in a large circuit with some redundant logic in it. The second step during synthesis, optimization, removes the redundant logic. You can see the final optimized circuit in the lower right hand corner.

You will remember that a process is the basic unit of execution in VHDL. There are two types of processes, combinatorial processes and sequential processes.

The basic structure of a process is the keyword PROCESS followed by a sensitivity list. Anytime a signal in the sensitivity list changes, the statements following the PROCESS statement, but before the END PROCESS statement are executed. We will look at an example process on the next slide.

A combinatorial process is sensitive to all inputs. If any signal changes, the process will execute again.

A sequential process is sensitive to a clock and or a control signals. If a process is sensitive to just a clock signal, a flip-flop is synthesized. In this way, only when the value of the clock signal changes, will the output change. We will see an example of this on the next slide

Here you can see a process statement. Notice that in this example, the sensitivity list contains only the clock. We also use the IEEE function rising edge. The process will only execute when the value of clock changes. Q gets D only when the rising edge function evaluates to true. This code synthesizes to a d-flip-flop.

Though they would synthesize to the same logic, they are different in simulation.

Here you can see a process statement. Notice that in this example, the sensitivity list contains only the clock. We also use the IEEE function rising edge. The process will only execute when the value of clock changes. Q gets D only when the rising edge function evaluates to true. This code synthesizes to a d-flip-flop.

Here you can see a process statement. Notice that in this example, the sensitivity list contains only the clock. We also use the IEEE function rising edge. The process will only execute when the value of clock changes. Q gets D only when the rising edge function evaluates to true. This code synthesizes to a d-flip-flop.

Here you can see a process statement. Notice that in this example, the sensitivity list contains only the clock. We also use the IEEE function rising edge. The process will only execute when the value of clock changes. Q gets D only when the rising edge function evaluates to true. This code synthesizes to a d-flip-flop.

You will often went to separate your design into multiple files.
Designing hierarchically in VHDL requires that you use components to connect your VHDL design units. In this example you can see that the top level top.vhd, references mid_a and mid_b. By referencing mid_a, top.vhd now has access to that entity.

A component declaration consists of the Component keyword followed by the lower level design name; the keyword IS and then port information.

After a component has been declared, you need to instantiate the component. The syntax is instance name colon lower level design name followed by the keyword PORT MAP. Within the port map section the lower level port names are mapped to current level port names.

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