Terasic is the leading developer and provider for FPGA-based hardware & complex system solution. With twenty years of experience in developing high-end solutions for the industrial and FPGA system markets, our team provides the first class design to order services for high speed boards and custom rugged system solutions to help our customers achieve their demanding applications in High performance computing, high frequency trading, network processing, radar detection, instrumentation, etc. Headquartered in Hsinchu, Taiwan, the silicon valley of Asia and the cradle of invention and creativity, Terasic boasts an extensive product portfolio from COTS of PCIe boards, high speed boards, FMC & HSMC daughter cards for networking & video processing to cost friendly educational & development kits widely used by today’s college education and worldwide research institutes. Our client include high performance computing, investment banks, data center, military & aerospace, medical & biomedical, robotic & automotive sectors, universities/ research institutions, etc.
Offerings
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Designed to address the applications requirements for embedded systems, robotics, and digital logics, the DE25-Standard development kit takes advantage of the Altera® Agilex™ 5 FPGA with 138K LEs to offer larger FPGA capacity and advanced feature sets such as 1GB DDR4 32-bit data bus, 64MB SDRAM, 8-channel ADC header, GPIO header, an HSMC high-speed connector, and black and light mini LCD, etc. A rich set of input and output features, such as robust switches, LEDs, seven-segment displays, and commonly-used I/O interfaces are included to meet the needs of teaching and experiments. In addition, the DE25-Standard is armed with the advanced HDMI output port (1080P), a two-lane MIPI CSI /DSI connector for camera and display, and a composite RCA jack for surveillance camera. Developers can leverage the AI tensor block on the Agilex™5 FPGA, the MIPI CSI/DSI connector, HDMI output, and the composite RCA jack on the DE25-Standard to develop AI-related applications such as video processing and computer vision.
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The Terasic Mercury A2700 accelerator card leverages the Intel® industry’s highest performance Agilex™ I-Series FPGA with 2700K logic elements to address the most compute and bandwidth-demanding applications in the data center, in the cloud, and in embedded devices. As the first Terasic accelerator that provides PCIe 5.0 x16 and Compute Express Link (CXL) support, the Mercury A2700 accelerator card enables 2X higher bandwidth compared with PCIe 4.0 interface for higher data throughput, as well as high-speed, low-latency, and efficient performance between CPU and FPGA. In addition, armed with two 200G QSFP-DD connectors, and four DDR4 SO-DIMM sockets, the Mercury A2700 accelerator card accelerates every workload across the data center and edge in computer vision, high performance computing, and other compute-intensive applications.
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The Atum A5 Development Kit is Terasic’s first development kit in the Intel® Agilex™ 5 FPGA portfolio. Powered by the largest Agilex® 5 SoC FPGA with 656K LEs, the Atum A5 Development Kit is an out-of-the-box platform for advanced AI and vision application development. With a rich set of interfaces ranging from 2.5G Ethernet, high-speed DDR4, QSFP+, PCIe Gen 3x4, FMC+ connectors, to MIPI connector and HDMI, the Atum A5 excels in a wide range of applications, including industrial networking, AI, embedded vision, medical and healthcare, video applications, and various other I/O expansion and high-speed applications!
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The Terasic DE5a-Net Arria® 10 GX FPGA Development Kit provides the ideal hardware solution for designs that demand high capacity and bandwidth memory interfacing, ultra-low latency communication, and power efficiency. With a full-height, 3/4-length form-factor package, the DE5a-Net is designed for the most demanding high-end applications, empowered with the top-of-the-line Intel® Arria 10 GX, delivering the best system-level integration and flexibility in the industry. The Arria 10 GX FPGA features integrated transceivers that transfer at a maximum of 12.5 Gbps, allowing the DE5a-Net to be fully compliant with version 3.0 of the PCI Express standard, as well as allowing an ultra low-latency, straight connections to four external 40G QSFP+ modules. Not relying on an external PHY will accelerate mainstream development of network applications enabling customers to deploy designs for a broad range of high-speed connectivity applications. For designs that demand high capacity and high speed for memory and storage, the DE5a-Net delivers with two independent banks of DDR3 SO-DIMM RAM, four independent banks of QDRII+ SRAM, high-speed parallel flash memory. The feature-set of the DE5a-Net fully supports all high-intensity applications such as low-latency trading, cloud computing, high-performance computing, data acquisition, network processing, and signal processing.
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Designed for modular and scalable high-performance FPGA Prototyping and HPC solutions, Apollo S10 SOM packs unbeatable performance and energy efficiency in a tiny form factor and provides up to 90X performance increase over CPUs for critical workloads such as simulation acceleration, molecular dynamics, machine learning.Apollo S10 SOM takes advantage of the latest Intel® Stratix® 10 SoC with 2800K logic elements to obtain speed and power breakthrough (with up to 70% lower power). Combining a number of high-end hardware interfaces such as high-capacity and high-bandwidth DDR4 SDRAM (up to 64GB), on-board USB-Blaster II, and FMC/FMC+ connectors for I/O expansion, the board delivers more than 2X the performance of previous generation development kits.Apollo S10 SOM is also extensible. Apollo Carrier board is designed to assist our clients development of Apollo S10 SOM. The carrier board features two ultra low-latency, straight connections 40Gbps QSFP+ module and Thunderbolt™ 3 for our clients’ to evaluate the I/O planned for their systems, and build their custom systems around it.
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Unlocking the power of AI and IoT is key to improving system engineering and accelerate innovation for today’s IoT development, ranging from Industry 4.0 to Vehicle-to-Anything (V2X). Purposely designed for the next-generation IoT innovation, Terasic’s TSOM enables outstanding flexibility and scalability to address the critical demand of IoT applications with its hardware and software programmability. TSoM is a pocket-sized module powered by the latest Intel® Cyclone® V SoC FPGA. The board itself takes advantage of the ARM dual-core Cortex-A9 CPU and 110K FPGA Logic Elements to achieve lowest system cost and power efficiency. Armed with 1GB DDR3 memory for FPGA and HPS fabric respectively, and up to 8GB eMMC flash, the Cyclone® V module ideally suited for building high bandwidth and large capacity memory system for a wide range of embedded applications. To achieve a developer friendly environment, an I/O based evaluation board is designed for users to experience the peripherals of the TSoM, to test and evaluate the I/O planned for their systems. Choose TSoM, and to improve overall equipment effectiveness with IoT data and AI.
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The traditional FPGA programming has proved problematic to most software engineers, yet the HERO platform provides a solution for everyone. In addition to the traditional professional programming model, the HERO platform customized BSP (Board Support Package) also supports OpenCL™-based flow development, providing a friendly programming interface for a wide range of algorithms and software programming for software engineers. For a customized system to support OpenCL™ flow, it requires FPGA hardware to provide complete data and control paths other than compatible software from the host. The OpenCL™ kernel can then be loaded dynamically in real time and run on the FPGA platform. To support OpenCL™ Flow, the full FPGA board support package has been ported to the HERO platform and is available as an integral part of the HERO SDK. The FPGA logic part of the existing HERO SDK BSP mainly includes a high-speed communication interface PCIe IP core, a memory DMA controller, an off-chip high-speed memory DDR4 interface, and a communication interface with the FPGA internal module. If users want to increase the speed of communications between the FPGA and the external interface, the HERO platform also has a corresponding BSP reference design that guides customers to implement a variety of flexible external interfaces for better and faster communication. The HERO platform has broad application prospects. Take the service robot as an example, its main role is to help people complete tasks and actions. To achieve this goal, R&D engineers need to implement a variety of complex applications on the robot, including vision, positioning, motion, and grabbing. FPGAs can be of great value in these critical applications, making the processing of complex algorithms efficient and real-time, giving users a good experience.
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Targeting the compute and acceleration needs from the edge to the core to the cloud, Terasic’s DE10-Agilex accelerator is purpose-designed to meet the ever-increasing demands for acceleration, compute, and fast data movement.The DE10-Agilex is based on the powerful Intel Agilex® FPGA to obtain speed and power breakthrough, with 40% higher performance, 40% lower power for equivalent performance. The accelerator includes PCI Express Gen 4.0 x16, two 200G QSFP-DD connectors and offers 32GB of DDR4 up to 680Gbps bandwidth to provide adaptable acceleration, maximum throughput and highly customizable processing of data for compute intensive applications.The DE10-Agilex fully supports Intel® OpenCL™ BSP and Intel® oneAPI Toolkits to provide optimal Computer Vision and Deep Learning solutions. Our clients' systems can achieve highest computing performance and lowest cost for their Data Center and AI applications by leveraging the Intel Agilex®FPGA on DE10-Agilex accelerator.
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Starter Platform for OpenVINO™ Toolkit is a PCIe based FPGA card with high performance and competitive cost. It's equipped with the largest Cyclone V GT（or GX）device at 301K LE and it supports PCIe Gen 2 x4(GX device will support PCIe Gen 1 x4). The board comes with 1GB DDR3, 64MB SDRAM, UART-to-USB interface, and extension headers such as GPIO and Arduino. This makes Starter Platform for OpenVINO™ Toolkit a re-configurable platform with adequate computing performance and low power consumption.The package of Starter Platform for OpenVINO™ Toolkit includes reference designs for all the peripherals onboard. It also has a detailed user manual for developers to follow and start building up a system according to their needs immediately.The Starter Platform for OpenVINO™ Toolkit is a perfect starting point as OpenCL HPC (High Performance Computing) development platform. It supports Intel FPGA OpenCL BSP for developers to design a system with high level programming language. The computation demanding tasks can be off-loaded from CPU to FPGA, resulting in significant system performance improvement.
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The DE10-Standard Development Kit presents a robust hardware design platform built around the Intel® System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system. Intel® SoC integrates an ARM -based hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The DE10-Standard development board includes hardware such as high-speed DDR3 memory, video and audio capabilities, Ethernet networking, and much more.
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The Video and Embedded Evaluation Kit - Multi-Touch for C5SoC Upgrade Kit, Second Edition( VEEK-MT2-C5SoC Upgrade Kit) offers customers who already own an Intel C5SoC board a brand new integrated platform to develop various embedded applications. We provide simple and straightforward installation guidelines for users to assemble their already owned C5SoC with this upgrade kit.With upgrade kit installed, this bundle also known as VEEK-MT2-C5SoC features an Intel C5SoC development board targeting the Cyclone V SoC FPGA, as well as a capacitive 7” TFT LCD with 800x480 resolution which natively supports 5 point touch and multi-touch gestures. A 8-megapixel digital image sensor with auto focus, ambient light sensor, Gyroscope, Magnetometer, and 3-axis accelerometer makes up the rich feature-set.The VEEK-MT2-C5SoC upgrade kit for C5SoC interfaces C5SoC board through HSMC interface. The kit provides customized HSMC cable and acrylics for C5SoC FPGA mainboard and MTLC2 LCD module to be assembled in a cubic form. The kit also provides useful reference designs for software developers to build comple embedded systems.
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TR5 FPGA development kit using the Intel® Stratix® V GX FPGA provides high-speed operation and transmission with large capacity up to 952K LE. The board provides four FMC connectors and a 2x20 GPIO connector. It offers a total of more than 500 I/Os for users to expand the usage with the peripherals connected. There are built-in high-speed DDR3 memory and SSRAM to increase the bandwidth for accessing large amounts of data for high-speed computation. In addition, the board also has PCIe and SATA interfaces for high-speed data transmission. The main applications of TR5 are ASIC prototyping validation and the establishment of prototype systems. The FMC connectors onboard are standard interfaces. Users can purchase or develop various FMC daughter cards to expand their system. For developers who need to use multiple FPGAs, they can leverage Terasic's FMC or PCIe cable to establish an inter-stackable multi-boards communication system. Users can also purchase Terasic PCIe daughter card to communicate with host PC. The TR5 development kit includes a variety of reference design examples for peripherals such as DDR3 SDRAM, SD card, USB-to-UART, SATA, PCIe, and an FMC connector. The kit is user friendly and enables users to quickly get started or verify the functions. The kit also provides a tool named "System Builder" software. It can automatically generate a complete Intel Quartus® Prime project including pin assignment and clock configuration IP upon users' selections of peripherals, FMC daughter cards, and a designated clock frequency. It helps users avoid time-consuming and error-prone manual pin-assignment work.
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The Video and Embedded Evaluation Kit - Multi-touch, Second Edition, on Cyclone V SoC Development Board (VEEK-MT2-C5SoC) is a comprehensive embedded design environment with everything developers need to create processing-based systems. VEEK-MT2-C5SoC delivers an integrated platform that includes hardware, design tools, intellectual property (IP) and reference designs to develop embedded solutions for a wide range of applications. The fully integrated kit allows developers to rapidly customize their processor and IP to best suit their specific application. The VEEK-MT2-C5SoC features the Intel Cyclone V SoC development board with Intel Cyclone V SX SoC FPGA and a capacitive 7" TFT LCD with 800x480 resolution which supports 5-point touch and multi-touch gestures. An 8-megapixel digital image sensor with autofocus, ambient light sensor, Gyroscope, Magnetometer, and 3-axis accelerometer makes up the rich feature-set. The all-in-one embedded solution offered on the VEEK-MT2-C5SoC, in combination with the LCD touch panel and digital image module, provides embedded developers the ideal platform for multimedia applications with unparallel processing performance. Developers can benefit from the use of this FPGA-based embedded processing system utilizing mitigating design risk and obsolescence, design reuse, reducing bill of material (BOM) costs by integrating powerful graphics engines within the FPGA, and by lower costs.
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Designed for high-performance AI-enabled edge solutions and HPC solutions, Apollo Agilex SOM packs unbeatable performance optimization and provides highest real-time compute/watts for edge AI applications. Apollo Agilex SOM takes advantage of the latest Intel Agilex® SoC with 1400K logic elements to obtain performance and power breakthrough (with up to 40% lower power than Stratix® 10 series). Combining high-end hardware interfaces such as two high-capacity and high-bandwidth DDR4 SO-DIMM Sockets (up to 32GB DDR4), on-board QSFP DD connector, PCIe Gen 4x16 up to 25.8 Gbps/ch with carrier, on-board USB-Blaster II, and FMC/FMC+ connectors for I/O expansion, the board delivers more than 2X the performance of previous generation development kits.
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The VEEK-MT2S Development Kit is a comprehensive embedded design environment with everything developers need to create processing-based systems. The VEEK-MT2S delivers an integrated platform including hardware, design tools, and reference designs for developing embedded software and hardware platforms in a wide range of applications. The fully integrated kit allows developers to rapidly customize their processor and IP to best suit their specific application. The VEEK-MT2S features a DE10-Standard development board targeting Intel® Cyclone® V SX SoC FPGA, as well as a capacitive LCD multimedia color touch panel which supports 5-point multi-touch and gestures. The all-in-one embedded solution offered on the VEEK-MT2S, in combination with LCD touch panel and digital image module, provides developers the ideal platform for multimedia applications with unparallel processing performance. Developers can benefit from the use of FPGA-based embedded processing system utilizing mitigating design risk and obsolescence, design reuse, reducing bill of material (BOM) costs by integrating powerful graphics engines within the FPGA. Please refer to the VEEK-MT2S Control Panel for SoC reference design in Linux touch-screen display.
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Terasic DE10-Lite is a cost-effective Intel® MAX® 10 based FPGA board. The board utilizes the maximum capacity Intel® MAX® 10 FPGA, which has around 50K logic elements (LEs) and on-die analog-to-digital converter (ADC). It features on-board USB-Blaster, SDRAM, accelerometer, VGA output, 2x20 GPIO expansion connector, and an expansion connector. The kit provides the perfect system-level prototyping solution for industrial, automotive, consumer, and many other market applications. The DE10-Lite kit also contains lots of reference designs and software utilities for users to easily develop their applications based on these design resources.
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Inspired by the demands of AI, Data Center, and High Frequency Trading, Terasic’s TR10a-LPQ (DDR4) is purpose-built for acceleration and high-speed connectivity applications to address the demands of the next-generation high-performance systems. The TR10a-LPQ is fully compliant with version 3.0 of the PCI Express standard, and supports ultra low-latency, straight connections to two external 40G QSFP+ modules. Also included are five ports of QDRII+ SRAM, high-speed parallel flash memory. Terasic partners with leading IP providers to offer cutting-edge solutions for financial, networking, and a variety of high-speed connectivity applications.
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The DE1-SoC Development Kit presents a robust hardware design platform built around the Altera System-on-Chip (SoC) FPGA, which combines hard processor system (HPS) with industry-leading programmable logic. Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system. Altera’s SoC integrates a hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The DE1-SoC development board includes hardware such as high-speed DDR3 memory, video and audio capabilities, Ethernet networking, and much more.The DE1-SOC Development Kit contains all components needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later ( 64-bit OS and Quartus II 64-bit are required to compile projects for DE1-SoC).
Offering
The HAN Pilot Platform Development Kit provides users a combination of ARM software and FPGA hardware development platforms. It has a vast memory device and peripherals on the hardware. This kit also includes resourceful reference designs to help users to accomplish their design needs. The hardware offers in the HAN Pilot Platform has the maximum capacity with 660K LEs in Arria®10 SoC FPGA and features various types of advanced multimedia interface such as: HDMI, DisplayPort, and 12G-SDI and a large capacity of DDR4 memory. The board high speed network interfaces, Gigabit Ethernet and 10GbE via SFP+ ports, provides hardware resources for applications related to network communication. The pre-installed 4GB DDR4 SO-DIMM module connected to the FPGA can be replaced and expanded up to 8GB in additIon to the onboard 1GB DDR4 memory module. Alternatively, this SO-DIMM socket can be used to connect Terasic QDR memory module to the FPGA for low latency applications. The High Pin Count FMC interface onboard is ideal for exploring the variety of functions through add-on daughter cards. The USB Type-C interface introduced for the first time is revolutionary and it offers USB 3.0 and DisplayPort connectivity, as well as bi-directional power delivery between the platform and host PC. The PCIe cabling socket at Gen 3 x4 can be connected to the host PC with Terasic PCIe x4 Cable Adapter (PCA) and PCIe cable to maximize the data transfer rate at lightening speed.
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The DE0-Nano board introduces a compact-sized FPGA development platform suited for prototyping circuit designs such as robots and ""portable"" projects. The board is designed to be used in the simplest possible implementation targeting the Intel® Cyclone® IV device up to 22,320 LEs. The DE0-Nano has a collection of interfaces including two external GPIO headers to extend designs beyond the DE0-Nano board, on-board memory devices including SDRAM and EEPROM for larger data storage and frame buffering, as well as general user peripheral with LEDs and push-buttons. The advantages of the DE0-Nano board include its size and weight, as well as its ability to be reconfigured without carrying superfluous hardware, setting itself apart from other general purpose development boards. In addition, for mobile designs where portable power is crucial, the DE0-Nano provides designers with three power scheme options including a USB mini-AB port, 2-pin external power header, and two DC 5V pins.
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The TR5-Lite Stratix® V FPGA Development Kit a slim form-factor PCIe board that features maximum power in a minimum size. Perfect for 1U chassis servers and other stringent environments, the TR5-Lite includes high speed SFP+ interfaces and high-bandwidth memory architecture for high performance computing, cloud systems, and ultra low-latency trading.
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The Terasic TR10a-HL2 Arria 10 GX FPGA Dev. Kit provides the robust hardware solution for designs that demand high capacity and bandwidth memory interfacing, ultra-low latency communication, and power efficiency. Powered by the top-of-the-line Intel Arria 10 GX, the full-height, half-length accelerator aims at delivering the best system-level integration and flexibility to the industry. The Arria® 10 GX FPGA features integrated transceivers that transfer at a maximum of 12.5 Gbps, allowing the TR10a-HL2 to be fully compliant with version 3.0 of the PCI Express standard, as well as allowing an ultra low-latency, straight connections to four external 40G QSFP+ modules. Not relying on an external PHY will accelerate mainstream development of network applications enabling customers to deploy designs for a broad range of high-speed connectivity applications. For designs that demand high capacity and high speed for memory and storage, the TR10a-HL2 delivers with six independent banks of QDRII+ SRAM, high-speed parallel flash memory. The feature-set of the TR10a-HL2 fully supports all high-intensity applications such as low-latency trading, cloud computing, high-performance computing, data acquisition, network processing, and signal processing. The TR10a-HL2 has a PCIe x16 edge connector which includes two PCIe Gen3 x8 interfaces. Each interface is directly connected to the FPGA PCIe Hard IP. It allows one PCIe Gen3 x8 connection in standard PCIe slot or two PCIe Gen3 x8 connections in a PCIe bifurcation slot. With dual PCIe Gen3 x8 interfaces, the TR10a-HL2 board can provide double the throughput rate than that of the TR10a-HL board.
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The Terasic Developer Kit for Intel® Pathfinder for RISC-V takes advantage of the powerful Intel® Cyclone® IV FPGA to allow RISC-V cores and other IP to be instantiated on a FPGA. The board is armed with 128MB SDRAM running exclusively for RISC-V cores, an on-board USB Blaster circuit for RISC-V debugging and FPGA programming, as well as a rich multimedia interface for advanced project development, making it an excellent platform to jump start performance-driven and mission critical applications.Intel® Pathfinder, together with the Terasic Developer Kit, offers the ability to run industry leading operating systems and tool chains within a unified IDE without the need for external debug cables. As a result, customers can achieve lower cost and higher performance in the project development phase.
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The Cyclone V Starter Kit presents a robust hardware design platform built around the Altera Cyclone V GX FPGA, which is optimized for the lowest cost and power requirement for transceiver applications with industry-leading programmable logic for ultimate design flexibility. With Cyclone V FPGAs, you can get the power, cost, and performance levels you need for high-volume applications including protocol bridging, motor control drives, broadcast video converter and capture cards, and handheld devices. The Cyclone V Starter Kit development board includes hardware such as Arduino Header, on-board USB Blaster, audio and video capabilities and much more. In addition, an on-board HSMC connector with high-speed transceivers allows for an even greater array of hardware setups. By leveraging all of these capabilities, the Cyclone V Starter Kit is the perfect solution for showcasing, evaluating, and prototyping the true potential of the Altera Cyclone V GX FPGA.
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The TR4 Development Board provides the ideal hardware platform for system designs that demand high-performance, serial connectivity, and advanced memory interfacing. Developed specifically to address the rapidly evolving requirements in many high end markets for greater bandwidth, improved jitter performance, and lower power consumption, the TR4 is powered by the Stratix® IV GX device and supported by industry-standard peripherals, connectors and interfaces that offer a rich set of features that is suitable for a wide range of compute-intensive applications.The TR4 is supported by multiple reference designs and six High-Speed Mezzanine Card (HSMC) connectors that allow scaling and customization with mezzanine daughter cards. For large-scale ASIC prototype development, multiple TR4s can be stacked together to create an easily-customizable multi-FPGA system.
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The DE1-SoC-MTL2 Development Kit is a comprehensive design environment with everything embedded developers need to create processing-based systems. The DE1-SoC-MTL2 delivers an integrated platform including hardware, design tools, and reference designs for developing embedded software and hardware platforms in a wide range of applications. The fully integrated kit allows developers to rapidly customize their processor and IP to best suit their specific application. The DE1-SoC-MTL2 features a DE1-SoC development board targeting Intel® Cyclone® V SE SoC FPGA, as well as a capacitive LCD multimedia color touch panel which supports five-point multi-touch and gestures. The all-in-one embedded solution offered on the DE1-SoC-MTL2, in a combination of an LCD touch panel and digital image module, provides embedded developers the ideal platform for multimedia applications with unparallel processing performance. Developers can benefit from the use of FPGA-based embedded processing system such as mitigating design risk and obsolescence, design reuse, lowering bill of material (BOM) costs by integrating powerful graphics engines within the FPGA. For SoC reference design in Linux for touch-screen display, please refer to the DE1-SoC-MTL2 Control Panel.
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The MAX 10 NEEK from Terasic is a full featured embedded evaluation kit based upon the MAX10 family of Altera FPGAs. It offers a comprehensive design environment with everything embedded developers need to create a processing based system. The MAX 10 NEEK delivers an integrated platform that includes hardware, design tools, intellectual property and reference designs for developing a wide range of audio, video and many other exciting applications. The fully integrated kit allows developers to rapidly customize their processor and IP to suit their specific needs, rather than constraining their software around the fixed feature set of the processor. The all-in-one embedded solution, the MAX 10 NEEK, combines a 5-point LCD touch panel and digital image module that provides developers an ideal platform for multimedia applications, making the best use of the parallel nature of FPGAs.
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The T-Core presents a robust hardware design platform built around the Intel MAX 10 FPGA. It is well equipped to provide cost effective, single-chip solutions in control plane or data path applications and industry-leading programmable logic for ultimate design flexibility. With MAX 10 FPGA, you can get lower power consumption / cost and higher performance than previous generation. When you need high-volume applications, including protocol bridging, motor control drive, analog to digital conversion, and handheld devices, the T-Core is your best choice. The T-Core development board includes hardware such as on-board USB-Blaster II, QSPI Flash, ADC header, WS2812B RGB LED and 2x6 TMD expansion header. By leveraging all of these capabilities, the T-Core is the perfect solution for showcasing, evaluating, and prototyping the true potential of the Intel MAX 10 FPGA.T-Core also supports RISC-V CPU with on-board JTAG debug. It is an ideal platform for learning RISC-V CPU design or embedded system design.
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The FPGA Cloud Connectivity Kit combines the rich versatility of an Intel® Cyclone® V SoC FPGA with the benefits of cloud connectivity. Nowadays, it is easy to develop your own FPGA based application that can collect, analyze and react to data from IoT equipment. This development kit is certified with key cloud service providers (CSPs) such as Microsoft Azure and comes with open-source design examples that will take new users through the process of connecting an FPGA-based edge device to the cloud for the first time. The kit is based on the extremely popular Terasic DE10-Nano Kit and adds Wi-Fi and Bluetooth wireless communication as well as a wide range of sensors such as an ambient light, temperature and humidity sensors, accelerometer and gyroscope. The FPGA Cloud Connectivity Kit will enable users to put a flexible and reconfigurable FPGA at the heart of their next smart IoT edge design.
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With the rapidly-rising demand in today’s AI and compute-intensive applications, Terasic’s FLIK (FPGA Client Innovation Kit) is a compact, all-in-one, adaptable accelerator purpose-design to accelerate critical workloads such as data analysis, deep learning, and machine learning algorithms directly on laptops or everything portable! With a form factor slightly larger than a 2.5'' external hard drive, it can be placed vertically or horizontally to blend into various size-demanding environment. FLIK takes advantage of the powerful Intel® Arria ® 10 FPGA to enable higher speed data processing. The kit is armed with 8GB DDR4-2133 on-board memory, providing around 4GB data transfer via PCIe Gen 3 interface between FPGA and laptops or Host PC via Thunderbolt™ 3 port. Also, closely packed in an aluminum body with advanced thermal solution, FLIK takes care of the heat dissipation dynamically.FLIK fully supports Intel® Open VINO™ Toolkit, Intel® Acceleration Stack, and OpenCL in both Linux and Windows versions. Our clients can achieve highest computing performance, adaptability and lowest cost across broadest range of AI and Deep Learning workloads.
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The ADC-SoC is a SoC FPGA motherboard with dual-channel high-speed ADC. The main card is based on the Terasic DE0-Nano-SoC board with a built-in high-speed ADC circuit on the DCC (AD / DA Data Conversion Card) on top of the main card. This feature makes the board an ideal platform for systems that require high-speed ADC applications. The built-in ADC circuit uses SMA as the input interface. The circuit provides two channels, each with 14-bit resolution and a sample rate of up to 150 MSPS (Megasamples per Second).
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Developer Kit for OpenVINO ™ Toolkit is a PCIe based FPGA card with high performance and competitive cost. It's equipped with the largest Intel® Cyclone® V GT（or GX）device at 301K LE and it supports PCIe Gen 2 x4 (GX device will support PCIe Gen 1 x4). The board comes with 1GB DDR3, 64MB SDRAM, UART-to-USB interface, and extension headers such as GPIO and Arduino. This makes Starter Platform for OpenVINO ™ Toolkit a re-configurable platform with adequate computing performance and low power consumption. The package of Developer Kit for OpenVINO ™ Toolkit includes reference designs for all the peripherals onboard. It also has a detailed user manual for developers to follow and start building up a system according to their needs immediately. The Developer Kit for OpenVINO ™ Toolkit is a perfect starting point as OpenCL HPC (High Performance Computing) development platform. It supports Intel® FPGA OpenCL BSP for developers to design a system with high level programming language. The computation demanding tasks can be off-loaded from CPU to FPGA, resulting in significant system performance improvement.
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The Terasic DE5-NET PCIe Board is based on Intel® Stratix® V GX FPGA. The board provides an ideal hardware solution for a variety of high-speed connectivity applications. The major features of the DE5-NET board are: Intel® Stratix® V GX FPGA features integrated transceivers that transfer at a maximum of 12.5 Gbps Full-height, 3/4-length PCIe form-factor package allows ultra-low-latency, straight connections to 4 external 10G SFP+ modules. (An advantage which accelerates mainstream development of network applications.) 2 independent banks of DDR3 SO-DIMM socket 4 independent banks of Cypress QDRII+ SRAM or functional compatible SRAMS High-speed parallel flash memory with FPPx32 4 SATA ports and 1 RS422 expansion header PCIe Gen 3 x8 (includes Windows PCIe drivers) Support Intel® FPGA OpenCL™ BSP Terasic’s DE5-Net fully supports all high-level applications ranging from low-latency trading, cloud computing, high-performance computing, data acquisition to network processing and radar detection.
Offering
The Terasic TR10a-HL Acceleration Board is based on Intel® Arria® 10 GX FPGA with 1,150K LEs. The board is designed to accelerate networking and a broad range of high speed connectivity applications. The major features of the TR10a-HL board are: Intel® Arria® 10 GX FPGA with integrated transceivers that transfer at a maximum of 12.5 Gbps Full-height, 1/2-length form-factor package PCIe Gen 3 x8 Ultra low-latency, straight connections to four external 40G QSFP+ modules 6 independent 550 MHz QDRII+ SRAMs, each with 18-bit data bus at 72Mbit Fast passive parallel (FPP x32) configuration for the Flash memory Terasic’s TR10a-HL provides high-speed memory buffer for applications which demand low-latency data transfer. For example, low-latency trading, high-performance computing, network processing, cloud computing, and data acquisition.
Offering
The DE10-Nano Development Kit presents a robust hardware design platform built around the Intel System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system. Intel® SoC integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The DE10-Nano development board is equipped with high-speed DDR3 memory, analog to digital capabilities, Ethernet networking, and much more that promise many exciting applications. The DE10-Nano Development Kit contains all the tools needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later.
Offering
The Terasic Agilex 7 FPGA Starter Kit takes advantage of the latest Intel Agilex® 7 SoC FPGA F-Series devices with either 800K or 2.7M logic elements options, offering 50% higher fabric performance and 40% lower power consumption than equivalent Stratix® 10 devices. The Terasic Agilex 7 FPGA Starter Kit combines a number of high-end hardware interfaces such as PCI Express 4.0 x8, one 100G QSFP-28 connector, on-board HDMI 2.1 output, along with up to 16GB of DDR4, to provide optimal acceleration and throughput for compute-intensive applications. In addition, the on-board FMC+ connector makes the board extensible and can work with various daughter cards, such as Terasic’s HDMI-FMC , XTS-FMC , 12G SDI-FMC , and P16E-FMCP daughter card. The Agilex 7 FPGA Starter Kit also supports the Intel® one API and Intel® OpenCL. Developers can customize their own unique acceleration workloads effortlessly by leveraging the Intel Agilex® FPGA on the Terasic Agilex 7 FPGA Starter Kit.