Design Gateway Co., Ltd. specializes in developing Intellectual Property (IP) Cores and Solutions designed to simplify complex protocol processing without CPU intervention. With over 37 years of experience in FPGA design, we create hardware solutions optimized for high performance, simple usage, and minimal resource consumption. We offer Data Center and Edge Computing solutions including Data Storage (NVMe/SATA), Networking (TOE/UDP/EMAC), Security (tCAM/AES/TLS), and super low latency solutions for various market segments such as Aerospace, Medical, Industrial & Equipment, Finance and Telecommunication applications targeting FPGA platforms.
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SDLink is a high speed FPGA configuration module which stores data on microSD card. By swapping microSD, FPGA configuration data is accordingly updated. SDLink attaches 16GBytes SDHC microSD card which is unlimited capacity for FPGA configuration data. The cost performance is up to 1/1000 compared with the conventional configuration ROM. Conventional on-board flash memory takes several minutes for 42MBytes configuration data programming. SDLink just takes 3 seconds. Moreover, Easy to update logic in fields because SDLink does not require the programming cable any more. In prototype production, SDLink is very useful for testing the circuit data of various patterns in a short time, and then you can change to standard configuration ROM when mass-producing. SDLink can remove microSD after configuration. After that, when microSD card insert again, SDLink start high-speed configuration immediately. It is useful for updating circuit data without system shutdown. Design Gateway provides free schematic check for SDLink users. You just send configuration part of the schematic to make sure the circuit design.
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IP Lock is FPGA logic security system which used very reliable AES encryption technology. IP properties in FPGA are protected from illegal copy by only including IP Lock in FPGA and connecting with encryption controller chip.
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tCAM-IP is a high performance, extremely low latency and highly configurable ternary content-addressable memory IP. tCAM-IP can make deterministic search at 400MSPS continuously speed with constant latency at 7 clock cycles. It can achieve matching/filtering performance at 400,000,000 packets per second over 40G/100G Ethernet. It is ideal for variant applications such as network packet filtering/forwarding, intelligent switch/router, deep packet inspection and network security application. We can provide tCAM-IP custom reference design together with TOE-IP, UDP-IP, EMAC-IP based on customer requirements.
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SHA-256 IP is an optimized and efficient implementation of a secure hash algorithm SHA-256 specified in FIPS 180-4 standard. SHA256-IP can process 512-bit data blocks in just 65 clock cycles. Delivering 7.875Mbps throughput per 1MHz clock such as 2.362 Gbps throughput @ 300MHz. SHA-256 is one of the most secure and practically unbreakable hashing functions which is most popular to use in various applications such as secure password hashing, digital signature, SSL/TLS certificate and Bitcoin cryptocurrency. Together with Design Gateway's data storage and networking IP, SHA256-IP enables more opportunity for inventing the secure, efficient and high performance applications.
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AES256 IP is 1st member of Advanced Encryption Standard (FIPS-197) IP Series, designed to support ECB mode for both encryption and decryption. AES256-IP computes 128-bit data blocks within constant 15 clock cycles. Delivering 8.53Mbps throughput per 1MHz such as 3.41 Gbps @400MHz.
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AES-256SS IP specializes in ultra-high throughput and ultra-low latency. IP computes 128-bit data blocks in every 1 clock cycle. Delivering 128Mbps throughput per 1MHz such as 51.2 Gbps @ 400MHz.
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AES-128 IP is 1st member of Advanced Encryption Standard (FIPS-197) IP Series, designed to support ECB mode for both encryption and decryption. AES128-IP computes 128-bit data blocks within constant 11 clock cycles. Delivering 11.6Mbps throughput per 1MHz such as 4.65 Gbps @400MHz.
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exFAT-IP for NVMe is integrated with Design Gateway's NVMe IP and low layer hardware for PCIe interface. The IP core is an ideal to access NVMe device as exFAT file system with ultra speed performance, similar to raw data access. This solution fits the application which needs to record data to NVMe device by FPGA. The data file is read by other hosts such as PC based on file system format.
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SATA Host IP Core operating with DG SATA-IP and SATA PHY is ideal for the storage system which does not have internal CPU to control SATA Device access. It is recommended to use in very high-speed data recording system, and RAID controller.
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USB3.0 (Host) IP Core is ideal for use in a USB3.0 supported device system which require high bandwidth up to 5.0Gbps. This IP Core will process almost all USB3.0 protocols by hardware. It achieves processing by low-end CPU. This IPcore provide link layer, protocol layer. Physical layer interfaces to PHY chip by TI. DesignGateway provide 1-hour limited sof file for Intel® FPGA development kits. You can evaluate the performance before purchasing the IP core. More information from here http://www.dgway.com/USB3-IP_A_E.html
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NVMe IP core is standalone NVMe Host Controller with built-in optimized PCIe Bridge and Internal Memory Buffer, designed to handle NVMe Protocol without CPU/OS and External DDR memory. It’s recommended for the application which requires high performance, high storage capacity, very compact system size and easily to support multiple NVMe SSDs.
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40GbE TCP Off-loading Engine(TOE40G-IP) IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE40G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for Intel® FPGA. It helps you to reduce development time. Design Gateway provide demo file for Intel® FPGA boards. You can evaluate TOE40G-IP core on real board before purchasing.
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TCP Offloading Engine(TOE1G) IP core is the epochal solution implemented without CPU. Usually TCP processing is complicated and needs an expensive high-end CPU. Because TOE1G IP core automatically takes over all functions of TCP/IP protocol which needs high-speed operation by hardware logic only. This IP product includes reference design for Intel® FPGA. It helps you to reduce development time. DesignGateway provide demo file for Intel® FPGA Development Kits for evaluation. You can evaluate TOE1G IP core on real board before purchasing.
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NVMeTCP25G IP is the standalone host side NVMe Over Fabric (NVMe/TCP) controller with no CPU and external memory required. Enabling very high-performance remote access to NVMe-oF Storage Server by simple user logic. Greatly reduce design complexity and development time. Allowing your FPGA Card/Board to get access to the existing NVMe-oF storage infrastructure remotely and directly over FPGA’s network interface with maximum possible performance. This IP core license includes the reference design for Intel® FPGA boards. It helps you to reduce development time and cost.
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10GbE TCP Offloading Engine(TOE10G-IP) IP core is the epochal solution implemented without CPU. Usually TCP processing is complicated and needs an expensive high-end CPU. Because TOE10G-IP core automatically takes over all functions of TCP/IP protocol which needs high-speed operation by hardware logic only. This IP product includes reference design for Intel® FPGA. It helps you to reduce development time. DesignGateway provide demo file for Intel® FPGA boards. You can evaluate TOE10G-IP core on real board before purchasing.
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Random Access & Multi User NVMe IP (rmNVMe-IP) is very high performance NVMe host controller which is highly optimized for high-IOPS random access applications. rmNVMe-IP supports multiple user interfaces, each user can simultaneously read/write to a single NVMe SSD at the same time. This IP is designed for the application that requires very random access performance such as real-time sensors data fusion and processing, OS file systems offloading and NVMe SSD tester. By pure hardware logic implementation, rmNVMe-IP is best in class in energy efficient, high performance and low FPGA resource usages for next generation applications.
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DG 10GbE MAC core implements the MAC layer for TOE/UDP10G-IP core. It is fully compatible with Intel® MAC core. It achieves super low latency and high-speed networking system.
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SATA AHCI IP core operating with SATA IP Core is suitable for the system which has the processor running on OS and needs to have SATA device to be the system storage. By using AHCI driver to access AHCI IP, the system can access SATA device with full features and high speed performance. ARM on Cyclone® V, Arria® V. Arria® 10 SoC platform can be used to be the processor for AHCI IP, so the IP can be applied for embedded storage system, RAID application, high-speed and large capacity data acquisition systems.
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25GbE TCP Offloading Engine(TOE25G-IP) IPcore is the epochal solution implemented without CPU. Usually TCP processing is complicated and needs an expensive high-end CPU. Because TOE10G-IPcore automatically takes over all functions of TCP/IP protocol which needs high-speed operation by hardware logic only. This IP product includes reference design for Intel® FPGA. It helps you to reduce development time. DesignGateway provide demo file for Intel® FPGA boards. You can evaluate TOE25G-IPcore on real board before purchasing.
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NVMe-IP Gen5 is a high-performance NVMe host controller IP designed for use with FPGAs. It provides direct access to the latest NVMe Gen5 SSD storage technology without the need for an external CPU or memory. It is a solution for ultra-high-speed data storage, with speeds of up to 16Gbytes/sec line rate per SSD, making it ideal for transferring massive files, delivering high-quality content, and recording high bandwidth and throughput data rates.
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NVMeTCP10G IP is the standalone host side NVMe Over Fabric (NVMe/TCP) controller with no CPU and external memory required. Enabling very high-performance remote access to NVMe-oF Storage Server by simple user logic. Greatly reduce design complexity and development time. Allowing your FPGA Card/Board to get access to the existing NVMe-oF storage infrastructure remotely and directly over FPGA’s network interface with maximum possible performance. This IP core license includes the reference design for Intel® FPGA boards. It helps you to reduce development time and cost.
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NVMeSW IP Core integrated with Avalon-ST PCIe Hard IP from Intel (PCIe hard IP) is ideal to access NVMe SSD without CPU and external memory such as DDR. NVMeSW IP can access more than one SSD through PCIe switch, as shown in Figure 1. By designing Arbiter including the FIFO for bufferring the data, multiple user logics can be accessed the different NVMe SSDs through one set of NVMeSW IP, PCIe hard IP and PCIe switch. As a result, each SSD can store the different data stream from the different data source at very high performance. For more specific applications, we also provides alternative IP as follows.
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M.2-FMC adapter board for NVMe-IP evaluation. Able to connect 2 NVMe SSDs. Suitable for NVMe 2ch RAID0 system on Intel® FPGA development kits.
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The FMC SATA RAID board [AB09-FMCRAID] is compliant with FMC standard and provides 10 SATA channels at maximum by high speed serial interface in HPC (High Pin Count)-FMC so that user can build SATA RAID prototype system. This board supports Intel® FPGA Development Kits and suitable with RAID system development with SATA-IP core provided by Design Gateway.
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AES256-GCM-10G25G IP core implement the advanced encryption standard (AES) with 256-bit key in Galois/Counter Mode (GCM) which is widely used for authenticated encryption with associated data (AEAD) application. This IP core can achieve high throughput 30.72 Gbps @240MHz, suitable to work together with our TOE10G IP or TOE25G IP core for high performance and secure communication applications.
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AES256-XTS IP Core (AES256XTS IP) implement the advanced encryption standard (AES) with XEX tweakable block cipher with ciphertext stealing (XTS) which is widely used in protecting the confidentiality of data on storage devices.
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AES256-GCM-100G IP core implement the advanced encryption standard (AES) with 256-bit key in Galois/Counter Mode (GCM) which is widely used for authenticated encryption with associated data (AEAD) application. This IP core can achieve high throughput 112.64 Gbps @220MHz, suitable to work together with our TOE100G IP core for high performance and secure communication applications.
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AES256-XTS-STG IP implement the advanced encryption standard (AES) with XEX (XOR Encrypt XOR) tweakable block cipher which operates sequences of complete blocks and is widely used in protecting the confidentiality of data on various storage devices with interfaces such as NVMe and SATA.
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AES256-XTS-STG-2X IP implement the advanced encryption standard (AES) with XEX (XOR Encrypt XOR) tweakable block cipher which operates sequences of complete blocks and is suitable for protecting the confidentiality of data on NVMe Gen4 storage devices.
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AES256-XTS-STG-4X IP implement the advanced encryption standard (AES) with XEX (XOR Encrypt XOR) tweakable block cipher which operates sequences of complete blocks and is suitable for protecting the confidentiality of data on NVMe Gen5 storage devices.
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TLS1.3 IP (Transport Layer Security IP) is the CPU-less & High-performance TLS v1.3 protocol engine for FPGA Acceleration with no CPU and external memory required. Providing maximum Gigabit Ethernet throughput for highly secure data transmission over 1G/10G/25G/100G network. Protect your valuable data from potential security breaches by using TLS secure transmission now! Especially, in Industrial IoT & Automation, Aerospace & Defense Applications.The TLS 1.3 IP core demo can successfully demonstrate very high throughput HTTPS upload and download with standard web server by pure hardware logic on FPGA.
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UDP10G IP core is the epochal solution implemented without CPU. This IP core is suitable for network application. This IP product includes reference design for Intel® FPGA. It helps you to reduce development time. DesignGateway provide demo file for Intel® FPGA boards. You can evaluate UDP10G-IP core on real board before purchasing.
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PCIe Gen5 SSD support, M.2-PCIe adapter board for NVMe-IP evaluation . Able to connect 4 NVMe SSDs.
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100GbE TCP Off-loading Engine(TOE100G-IP) IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE100G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for Intel® FPGA. It helps you to reduce development time. Design Gateway provide demo file for Intel® FPGA boards. You can evaluate TOE100G-IP core on real board before purchasing.