VESA® Display Stream Compression-M (VDC-M) 1.2 Encoder IP Core for Intel® FPGAs
About this offer
Key Features: VESA® Display Compression-M (VDC-M) 1.2 compliant. Supports all VDC-M encoding mechanisms o BP, transform, MPP, MPP fallback, and BP skip o Flatness detection and signaling. Configurable maximum display resolution of up to 16Kx16Ko Typical 4K (4096x2160), 5K UHD+, and 8K UHD supported, configurable compressed bit rate, in increments of 1/16 bitsper pixel (bpp) 8, 10, or 12 bits per component video 4:4:4 sampling for RGB video input format 4:4:4, 4:2:2, and 4:2:0 sampling for YCbCr video input formats Pixel throughput of two (2) pixels per clock per hard slice encoder. Parameterizable number of parallel slice encoder instances(1,2, 4, or 8) to adapt to the capability of the technology and target display resolutions used. Logical slice encoding (2 soft slices) in each physical encoder (hard slice), support for Intel® Arria®, Stratix®, and Agilex™ FPGAs • AXI-S (VPP-Lite) streaming interfaces for easy integration in the Intel® platform designer tool, Avalon memory-mapped interface for register access. Compliant solution for MIPI® DSI-2SM v1.1. Supports flexible usage models and design architecture.
Technical Specifications
- Category:
- Software and IP Cores: FPGA Intellectual Property Cores: Interface Protocols: Audio and Video
- End Customer Type:
-
Consumer
Small and Medium sized Business
Enterprise
Other
Resources
Included Intel Technology
Stratix® IV FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel Agilex® 7 FPGAs and SoC FPGAs
Stratix® III FPGAs
Stratix® FPGAs
Arria® V FPGAs and SoC FPGAs
Stratix® II FPGAs
Arria® FPGAs
Arria® II FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Stratix® V FPGAs
Rambus
Due to a technical difficulty, we were unable to submit the form. Please try again after a few minutes. We apologize for the inconvenience.
Rambus
The recaptcha has identified the current interaction similar to a bot, please reload the page or try again after some time.
Rambus makes industry-leading chips and IP that advance data center connectivity and solve the bottleneck between memory and processing. The ongoing shift to the cloud, along with the widespread advancement of AI across data center, 5G, automotive and IoT, has led to an exponential growth in data usage and tremendous demands on data infrastructure. Creating fast and safe connections, both in and across systems, remains one of the most mission-critical design challenges limiting performance in advanced hardware. Rambus is ideally positioned to address this challenge as an industry pioneer with over 30 years of advanced semiconductor interconnect experience moving and protecting data. We are a leader in high-performance memory subsystems, providing chips, IP and innovations that maximize the performance and security in data-intensive systems. Whether in the cloud, at the edge or in your hand, real-time and immersive applications depend on data transfer speed and trust. Rambus products and innovations deliver the increased bandwidth, capacity and security required to usher in a new era of data center architectures and drive ever-greater end-user experiences.
Vesa® Display Stream Compression-m (vdc-m) 1.2 Encoder Ip Core For Intel® Fpgas
Your request for information has been successfully sent to Rambus