DPSMBUS - SMBUS & PMBUS Master/Slave controller
About this offer
DPSMBUS is a fully-featured module based on the I2C protocol, which supports SMBus and PMBus functionalities. It can operate as a DPSMBUSM – Master and DPSMBUSS – Slave. Due to SMBus and PMBus documentation, the module meets requirements, both for SMBSDA and SMBSCK , for acceptable timing intervals. DSPMBUS module supports arbitration and clock synchronization, which is necessary for multi-master systems. The IP Core, as it’s been suggested in the SMBus documentation, has implemented a reaction on a stuck SMBSCK signal in a low state Ttimeoutmin.
Technical Specifications
- Category:
- Software and IP Cores: FPGA Intellectual Property Cores: Processors and Peripherals: Peripherals
- End Customer Type:
-
Enterprise
Resources
Included Intel Technology
Intel® Cyclone® 10 FPGAs
Intel® MAX® 10 FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
DIGITAL CORE DESIGN
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DIGITAL CORE DESIGN
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Digital Core Design is a leading Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house. The company was founded in 1999 and thanks to in-depth specialization and innovative approach we have introduced more than 70 different architectures. Among them you can find e.g. World’s Fastest 8051 CPU, World’s Smallest 8051 CPU, silicon proven and royalty-free 32-bit CPU, Automotive LIN, CAN, CAN-FD, CAN-XL controllers
Dpsmbus - Smbus & Pmbus Master/slave Controller
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