DFSPI – SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL and QUAD SPI Bus Controller with DDR / DTR support and optional AES Encryption)
About this offer
DFSPI bridge to APB, AHB, AXI bus, it is a fully configurable SINGLE, DUAL, QUAD, and OCTAL SPI master/slave device, which allows the user to configure polarity and phase of serial clock signal SCK. As an option, the DFSPI controller has built-in support for HyperBusTM specification and xSPI (Expanded Serial Peripheral Interface – JESD251A) specification. The SPI Controller allows easy communication with the most available SPI FLASH memories.A serial clock line (SCK) synchronizes the shifting and sampling of the information on the serial data lines. It is a technology-independent design that can be implemented in a variety of process technologies. The DFSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate the most available synchronous serial peripheral devices.The DFSPI can automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS3O – SS0O), and address SPI slave device to exchange serially shifted data. It supports two DMA modes: single transfer and multi-transfer. These modes allow DFSPI to interface to higher-performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers. DFSPI is fully customizable, which means it is delivered in the exact configuration that meets users’ requirements.
Technical Specifications
- Category:
- Software and IP Cores: FPGA Intellectual Property Cores: Processors and Peripherals: Peripherals
- End Customer Type:
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Enterprise
Consumer
Small and Medium sized Business
Included Intel Technology
Cyclone® V FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs
Stratix® V FPGAs
MAX® CPLDs
Intel® Cyclone® 10 FPGAs
Arria® FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
MAX® V CPLDs
MAX® II CPLDs
Intel® MAX® 10 FPGAs
Arria® V FPGAs and SoC FPGAs
DIGITAL CORE DESIGN
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Digital Core Design is a leading Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house. The company was founded in 1999 and thanks to in-depth specialization and innovative approach we have introduced more than 70 different architectures. Among them you can find e.g. World’s Fastest 8051 CPU, World’s Smallest 8051 CPU, silicon proven and royalty-free 32-bit CPU, Automotive LIN, CAN, CAN-FD, CAN-XL controllers
Dfspi – Spi Flash Controller With Execute In Place – Xip (single, Dual And Quad Spi Bus Controller With Ddr / Dtr Support And Optional Aes Encryption)
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