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D16950 - Expanded UART with FIFO, hard and soft flow control, synchronous mode

About this offer

D16950 bridge to APB, AHB, AXI bus, it is a soft core of a Universal Synchronous and Asynchronous Receiver/Transmitter (UART), functionally compatible to the OX16C950. It allows serial transmission in two modes: UART and FIFO. In the FIFO mode, internal FIFOs are activated allowing 128 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes. Our efficient Core performs serial-to-parallel conversion on data characters received from a peripheral device or MODEM, but also parallel-to-serial conversion on data characters received from the CPU. The processor can read a complete status of the UART at any time during the functional operation. The reported status information includes a type and condition of transfer operations performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt). The D16950 includes a programmable baud rate generator which is able to divide a timing reference clock input by divisors of 1 to (216-1) and produce a n × clock for driving internal transmitter logic. Provisions are also included to use this n × clock to drive receiver logic. We also equipped our core with complete MODEM-control capability and processor-interrupt system. Interrupts can be programmed in accordance to your requirements, minimizing computing required to handle the communications link. The D16950 core includes all (16450, 16550, 16650 and 16750) features and additional functions. The D16950 has ICR registers which give additional capabilities of UART work configuration. Data transmission may be synchronized by an external clock connected to the RI (for receiver and transmitter) or DSR (only for receiver) pin. The NMR register allows 9-bit mode transmission with or without special character. Writing and reading from/to FIFO may be controlled by trigger level registers. Trigger level registers may be set any value from 1 to 127. In the FIFO mode, there is a selectable autoflow control feature that can reduce software overload significantly and automatically increase system efficiency by controlling serial data flow through the RTS output and CTS input signals. The Core is perfect for applications where the UART core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip. Nevertheless, it’s also a proprietary solution for standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks to a universal interface, D16950 core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system. As all our UART Cores, the D16950 includes fully automated test bench with complete set of tests, allowing easy package validation at each stage of SoC design flow. This efficient solution is a technology independent design that can be implemented in variety of process technologies.

Details

Regional Coverage

Americas:
Latin America Region:
Panama
Nicaragua
Belize
Antigua and Barbuda
Cayman Islands
Bermuda
El Salvador
St. Vincent
Sint Maarten
Haiti
Suriname
St. Kitts and Nevis
Chile
Guadeloupe
Dominican Republic
Turks and Caicos
St. Lucia
Bahamas
Mexico
Guatemala
Curacao
Jamaica
Grenada
Uruguay
Falkland Islands
Peru
Brazil
Antarctica
Dominica
Aruba
Venezuela
Argentina
Honduras
Trinidad and Tobago
French Guiana
St. Barthelemy
Ecuador
Colombia
Guyana
Costa Rica
Paraguay
Martinique
Bolivia
St. Martin
Montserrat
Barbados
Anguilla

North America Region:
US Virgin Islands
Guam
Bonaire
US Minor Outlying Islands
American Samoa
British Virgin Islands
United States
Canada
Puerto Rico

Asia, Pacific, and Japan:
Southeast Asia:
Singapore
Brunei
Indonesia
Myanmar
Philippines
Malaysia
Vietnam
Timor-Leste
Thailand

Australia and New Zealand:
Heard Island and McDonald Islands
Australia
New Zealand

Japan:
Japan

Taiwan:
Taiwan

Rest of Asia:
French Polynesia
Samoa
Nepal
Christmas Island
Northern Mariana Islands
Kiribati
Vanuatu
Mongolia
Palau
Niue
Norfolk Island
Laos
Tuvalu
Cook Islands
South Georgia and the South Sandwich Islands
Nauru
Pitcairn
Tokelau
New Caledonia
Papua New Guinea
Tonga
Solomon Islands
Marshall Islands
British Indian Ocean Territory
Micronesia
Cocos Islands
Wallis and Futuna
Fiji
Afghanistan
Cambodia

Korea:
South Korea

South Asia:
Bhutan
India
Sri Lanka
Maldives
Bangladesh
Pakistan

Europe, Middle East, and Africa:
Middle East, Turkey, and Africa:
Madagascar
Congo (the Democratic Republic of the)
Qatar
Togo
Kuwait
Angola
State of Palestine
Morocco
Saudi Arabia
Bahrain
Cameroon
Zambia
Eswatini
Burundi
Algeria
Ghana
Mali
Gabon
Chad
Ethiopia
Benin
Liberia
Comoros
Burkina Faso
Libya
Egypt
Cape Verde
Tunisia
Cote d'Ivoire
Mozambique
Iraq
South Africa
Eritrea
Western Sahara
Mayotte
Oman
Congo
Sudan
Tanzania
Reunion
Equatorial Guinea
Mauritius
Namibia
Sao Tome and Principe
Kenya
Zimbabwe
Mauritania
Djibouti
Jordan
Bouvet Island
Guinea-Bissau
Turkey
St. Helena
South Sudan
Lesotho
Lebanon
United Arab Emirates
Guinea
Uganda
Nigeria
Botswana
Malawi
Senegal
Seychelles
Yemen
Central African Republic
Niger
Gambia
Somalia
Rwanda
Sierra Leone

Central Eastern Europe:
Slovakia
Macedonia
Slovenia
Bulgaria
Romania
Montenegro
Croatia
Serbia
Lithuania
Bosnia and Herzegovina
Czechia
Latvia
Estonia
Albania
Poland
Hungary

Western European Union Region:
Luxembourg
Monaco
Gibraltar
Guernsey
St. Pierre and Miquelon
Switzerland
Isle of Man
Liechtenstein
French Southern Territories
Jersey
Belgium
France
San Marino
Vatican City

Commonwealth of Independent States:
Georgia
Armenia
Turkmenistan
Kyrgyzstan
Uzbekistan
Ukraine
Moldova
Tajikistan
Azerbaijan
Kazakhstan

Northern European Union Region:
Svalbard and Jan Mayen
Finland
Greenland
Denmark
Iceland
Ireland
Netherlands
United Kingdom
Norway
Aland Islands
Sweden
Faroe Islands

Southern European Union Region:
Greece
Portugal
Cyprus
Andorra
Malta
Italy
Israel
Spain

Central European Region:
Germany
Austria

People's Republic of China:
People's Republic of China:
Macao
Hong Kong
Mainland China

Use Case

Smart City

Smart Building

Others

Digital Security Surveillance

Health & Life Sciences

Situational Monitoring

Artificial Intelligence

Robot

Smart Home

Industry

Energy and Utilities

Health and Life Sciences : Clinical Systems

Health and Life Sciences : Medical Devices

Health and Life Sciences : Medical Imaging

Health and Life Sciences : Patient Infotainment

Manufacturing : Automotive

Manufacturing : Industrial Automation

Manufacturing : Transportation Equipment

Defense and Space

Automotive : Autonomous Driving

Automotive : In Vehicle Infotainment

Manufacturing : Automotive

Technical Specifications

Category:
Software and IP Cores: FPGA Intellectual Property Cores: Processors and Peripherals: Peripherals
End Customer Type:

Enterprise

Consumer

Small and Medium sized Business

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Resources

D16950 webpage
Resource Type: URL
Published On: Feb 22, 2023
D16950
Resource Type: Data Sheet
Published On: Feb 22, 2023

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DIGITAL CORE DESIGN

Digital Core Design is a leading Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house. The company was founded in 1999 and thanks to in-depth specialization and innovative approach we have introduced more than 70 different architectures. Among them you can find e.g. World’s Fastest 8051 CPU, World’s Smallest 8051 CPU, silicon proven and royalty-free 32-bit CPU, Automotive LIN, CAN, CAN-FD, CAN-XL controllers

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D16950 - Expanded Uart With Fifo, Hard And Soft Flow Control, Synchronous Mode

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