DI2CS - I2C Bus Interface - Slave
About this offer
DI2CS bridge to APB, AHB, AXI bus, provides an interface between a microprocessor/microcontroller and I2C bus. It can work as:a slave transmitter orslave receiverdepending on a working mode determined by the master device. The DI2CS core incorporates all features required by the latest I2C specification, including:clock synchronization,arbitration,high-speed transmission mode.The DI2CS supports all transmission speed modes:Standard (up to 100 kb/s)Fast (up to 400 kb/s)Fast Plus (up to 1 Mb/s)High Speed (up to 3,4 Mb/s)DCD’s IP Core is a technology-independent design and can be implemented in various process technologies.
Technical Specifications
- Category:
- Software and IP Cores: FPGA Intellectual Property Cores: Processors and Peripherals: Peripherals
- End Customer Type:
-
No
Resources
Included Intel Technology
Intel® Arria® 10 FPGAs and SoC FPGAs
DIGITAL CORE DESIGN
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DIGITAL CORE DESIGN
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Digital Core Design is a leading Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house. The company was founded in 1999 and thanks to in-depth specialization and innovative approach we have introduced more than 70 different architectures. Among them you can find e.g. World’s Fastest 8051 CPU, World’s Smallest 8051 CPU, silicon proven and royalty-free 32-bit CPU, Automotive LIN, CAN, CAN-FD, CAN-XL controllers
Di2cs - I2c Bus Interface - Slave
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