DHDLC - HDLC/SDLC controller
About this offer
DHDLC bridge to APB, AHB, and AXI bus, provides versatile support for a widely used HDLC transmission protocol. It manages the bit stuffing process, both address appending and detection. And if it’s not enough, let’s just mention that DCD’s IP Core supports CRC16 and CRC32 computation. Increased system performance and reduced CPU overload are a must-be, thanks to the presence of separate receiver and transmitter FIFO buffers, maskable interrupt, and DMA interface requests. The DHDLC is a fully scalable IP Core, which makes it a perfect solution for both high-end and deeply embedded projects.
Technical Specifications
- Category:
- Software and IP Cores: FPGA Intellectual Property Cores: Processors and Peripherals: Peripherals
- End Customer Type:
-
No
Resources
Included Intel Technology
DIGITAL CORE DESIGN
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DIGITAL CORE DESIGN
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Digital Core Design is a leading Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house. The company was founded in 1999 and thanks to in-depth specialization and innovative approach we have introduced more than 70 different architectures. Among them you can find e.g. World’s Fastest 8051 CPU, World’s Smallest 8051 CPU, silicon proven and royalty-free 32-bit CPU, Automotive LIN, CAN, CAN-FD, CAN-XL controllers
Dhdlc - Hdlc/sdlc Controller
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