DI2CSB - I2C Bus Interface Slave -Base version
About this offer
DI2CSB bridge to APB, AHB, and AXI bus, provides an interface between a passive target device e.g. memory, LCD display, pressure sensors, etc., and the I2C bus. It can work as a slave receiver or transmitter depending on a working mode determined by the master device. A very simple interface, composed of reading, write, and data signals, allows easy connection to target devices. The core does not require any programming and is ready to work after power-up/reset. Read, write, burst read, burst write and repeated start transmissions are automatically recognized by the core. The solution incorporates all features required by the I2C specification
Technical Specifications
- Category:
- Software and IP Cores: FPGA Intellectual Property Cores: Processors and Peripherals: Peripherals
- End Customer Type:
-
Enterprise
Resources
Included Intel Technology
Intel® Arria® 10 FPGAs and SoC FPGAs
DIGITAL CORE DESIGN
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DIGITAL CORE DESIGN
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Digital Core Design is a leading Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house. The company was founded in 1999 and thanks to in-depth specialization and innovative approach we have introduced more than 70 different architectures. Among them you can find e.g. World’s Fastest 8051 CPU, World’s Smallest 8051 CPU, silicon proven and royalty-free 32-bit CPU, Automotive LIN, CAN, CAN-FD, CAN-XL controllers
Di2csb - I2c Bus Interface Slave -base Version
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