AES 128 IP
About this offer
AES-128 IP is 1st member of Advanced Encryption Standard (FIPS-197) IP Series, designed to support ECB mode for both encryption and decryption. AES128-IP computes 128-bit data blocks within constant 11 clock cycles. Delivering 11.6Mbps throughput per 1MHz such as 4.65 Gbps @400MHz.
Technical Specifications
- Category:
- Software and IP Cores: FPGA Accelerator Functions: Networking and Security
- End Customer Type:
-
Small and Medium sized Business
Enterprise
Resources
Included Intel Technology
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Stratix® V FPGAs
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Intel Agilex® 7 FPGAs and SoC FPGAs
Intel Agilex® 9 FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs
Cyclone® V FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
DESIGN GATEWAY
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Design Gateway Co., Ltd. specializes in developing Intellectual Property (IP) Cores and Solutions designed to simplify complex protocol processing without CPU intervention. With over 37 years of experience in FPGA design, we create hardware solutions optimized for high performance, simple usage, and minimal resource consumption. We offer Data Center and Edge Computing solutions including Data Storage (NVMe/SATA), Networking (TOE/UDP/EMAC), Security (tCAM/AES/TLS), and super low latency solutions for various market segments such as Aerospace, Medical, Industrial & Equipment, Finance and Telecommunication applications targeting FPGA platforms.
Aes 128 Ip
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