Arik Gihon
Lead power management architect for 12th Gen Intel Core processors
Modern microchips are enormously complex — to design, to build and even to understand. At the same time, they’re also fairly simple: Electrical signals go in, something happens inside and electrical signals come out. That’s really it.
From that power-in/power-out perspective, chip architect Arik Gihon has tremendous influence. Based at Intel’s Israel design center, Gihon is the lead power management architect of the 12th Gen Intel® Core® processor family, code-named “Alder Lake.”
Power management means constantly juggling a feverishly changing set of demands: supporting all the different things a user is trying to do with their computer, keeping temperature in check, preserving battery life — and doing it all as quickly as possible.
Manage the Power, Control the Chip
By controlling the power, “we’re basically defining the way the CPU behaves,” Gihon confirms.
The job is only getting more complex. Demands compete — you can send more power to a part of the chip to make things go faster for the user at the cost of more heat and battery usage — and face increasing physical constraints. As the internal building blocks of chips get smaller following Moore’s Law, for instance, the number of components per area goes up, making heat management harder. (The current, or flow of electricity, through a modern fingernail-sized chip can surpass that of an entire house, Gihon says, though at much lower voltage.)
And leading-edge silicon is expensive, so every square millimeter comes at a premium. “Area is money,” Gihon says.
Luckily, Intel has plenty of ingenuity to throw at the complexity. Right now, “it’s extremely exciting to be an architect,” Gihon says. His toolbox spans process technologies, architecture, software, packaging, memory and more. Add to that a companywide push “to do big things” in a world of intensified competition and “you can almost do anything.”
A New Kind of Hybrid Puts Performance First
Anything, say, like introducing the new “performance hybrid” architecture that is coming with 12th Gen Core. The new chips combine two sets of processing cores: small Efficient-cores (or E-cores) that easily multiply to handle multiple jobs at once, and larger Performance-cores (P-cores), each with more per-core performance than anything Intel has produced to date1.
Press Kit: 12th Gen Intel Core
Unlike other hybrid approaches, Gihon says, the goal was not maximum efficiency — with performance secondary — but rather maximum performance. He explains that adding a large number of Performance-cores would achieve performance but lead to a chip simply too large. The Efficient-cores bring as much performance as 10th generation Performance-cores at less power and dramatically less area.
“You can add up a lot of them and then you get quite a lot of cores and you can scale multi-threaded applications,” Gihon says. “So together with that you can also go to the Performance-core team and tell them, ‘You know what? Now that I’ve solved the scaling of the amount of cores for multi-threading, then now go do your best in single-thread performance. You have less limitation on area.’”
That they did. The result is a single chip with both a set of super-cores for the most demanding jobs and another set of smaller-yet-still-fast cores for handling lots of simultaneous work.
As enticing as this no-compromise approach sounds today, Gihon says it sparked a series of debates among engineers and technical leaders. If “hybrid” makes you think of a platonic car that sheds the range anxiety of an all-electric at the expense of a more thrilling drive, well, some of the team felt that way, too.
The Art of Chip Design: Complexity Versus Value
But overcoming skepticism is part of the job when designing a system-on-chip (SoC). “SoC architects need to love the wide view of things, the big picture… [and they] need to like convincing people, giving a lecture,” Gihon explains. “If you have a vision, sometimes only after you explain things do you really understand what you want it to do.” Adding smaller E-cores for performance “took time to digest.”
After teams got the green light, the real work began: designing not just a new chip for desktop PCs but the full range for the PC market, notably laptops, 2 in 1s and mobile designs. “The architecture is built in a way that you can scale them up and down with building blocks,” Gihon says, mixing and matching said blocks for each scenario.
“It’s like building a puzzle,” he explains, “but instead of just connecting the parts, you need to put the puzzle parts far from each other and then build the complete highway network between the different parts so they will all work together. You need to do that in a way that satisfies many vectors.”
“We always have to debate between complexity and value,” he adds. “This is the artwork to balance.”
But the challenges don’t end when the design is done.
Welcome to ‘the Exciting Part’
“Every generation, after we have produced the silicon, we have learned or had to deal with new challenges that we did not know before,” he notes. “This is the exciting part! Sometimes the simulations do not reflect the physics well enough and you need to adjust things only after you see the silicon.”
“It’s a rapid world,” Gihon says. “Things are changing quite fast — software is changing, the amount of data is exploding.”
Predicting the future is only getting harder, and he’s responded by picking up his own pace. Prior to the pandemic, he explains, he did his best thinking on his 45-minute commute by train. Now he runs every day. “I’m doing distance runs like 10 kilometers, 20, and even reach 40 and the marathon. On Saturday long runs, I have hours of thinking with myself.”
Squeezing maximum performance out of a fixed amount of power, Gihon is in his element — even on a run.