What is Altera Innovators Day?
Altera Innovators Day is the re-envisioned Intel FPGA Technology Day (IFTD). This annual event showcases Altera's FPGA technology and solutions, the latest announcements, and frequently requested sessions such as developer productivity and getting started with FPGAi. You’ll also hear from our customers and partners on their perspectives about FPGA challenges and accomplishments.
Why Attend?
Hear the breaking news, get access to our top technical engineering innovators, and learn how to unleash your innovative ideas. Gain insights into how Altera’s broad FPGA portfolio delivers solutions across a wide variety of markets, from the cloud to the edge. See and interact with our experts showing live demonstrations based on high-performance, mid-range, and cost-effective products and FPGAi.
Space is limited, let us know your interest today!
Meet Our Keynote Speakers
Sandra Rivera, CEO, Altera Corporation
Sandra Rivera, CEO, Altera Corporation
Sandra Rivera is the CEO of Altera. She has nearly four decades of engineering and leadership experience in the semiconductor, communications, and networking industries. Before assuming her current role, Sandra spent 23 years at Intel Corporation, most recently leading its Data Center and AI Group. There, she drove Intel’s overall AI strategy and guided the development of data center products, including FPGAs, CPUs, GPUs, and AI accelerators. In 2023, TIME Magazine named Sandra one of the industry’s most influential people in AI. Sandra holds a bachelor’s degree in electrical engineering from Pennsylvania State University. She sits on the Equinix board of directors and is a member of the University of California, Berkeley’s engineering advisory board.
Mahesh Iyer, Senior Fellow, Altera Corporation
Mahesh Iyer, Senior Fellow, Altera Corporation
Mahesh Iyer is an Intel Senior Fellow and chief EDA software & FPGA architect at Altera. Before joining Altera and Intel, Iyer was with Synopsys Inc. serving as the chief software architect for Synopsys’ flagship products, Design Compiler, IC Compiler, and VCS. Iyer holds a Ph.D. in electrical engineering from the Illinois Institute of Technology and has authored 40+ papers and 100+ patents. He was named a Synopsys Fellow in 2006, an Altera Fellow in 2013, an Intel Fellow in 2016, an Intel Senior Fellow in 2021, and an IEEE Fellow in 2021.
Ilya Ganusov, Fellow, Altera Corporation
Ilya Ganusov, Fellow, Altera Corporation
Dr. Ilya Ganusov leads FPGA Architecture definition at Altera. He joined Intel in 2018 to lead Agilex™ FPGA core architecture development and definition of application-specific optimizations for AI, HPC, and wireless communication applications. He has co-authored over 40 granted patents and dozens of publications and presentations on FPGA architectures, CAD algorithms, prefetching in memory hierarchies, and circuit design. Ilya received his Ph.D. degree in Electrical and Computer Engineering from Cornell University.
Peng (Mike) Li, Fellow, Altera Corporation
Peng (Mike) Li, Fellow, Altera Corporation
Dr. Peng (Mike) Li is an Intel Fellow and the Chief Technologist on SerDes, high-speed I/O (HSIO), and interconnects/platforms at Intel PSG/Atera, co-driving/leading Intel/Altera SerDes, HSIO, and interconnect/platforms strategy and roadmap, as well as industry standards, SerDes and HSIO architecture; electrical and optical signaling, silicon photonics integration; and optical field-programmable gate arrays (OFPGAs). Li joined Intel in 2015 with the acquisition of Altera Corp., where he had held a similar role as an Altera Fellow since 2012.
Join Us For a Day of Learning, Collaborating, and Reimagining Together
We are live in at Santa Clara Convention Center
Event Schedule
7:30am – Check-in and Breakfast
8:30am – Opening Keynote: Unleash Your Innovation
9:15am – Add AI with Hardware and Software Flexibility
12:30pm – Lunch and Learn with the Innovators
3:15pm – Connect Applications at 116 Gbps Today, and 224 Gbps in the Near Future
4:00pm – Closing Keynote: Partner with the Best
4:15pm – Demo Showcase/Happy Hour/Meet the Innovators
5:15pm – Attendee Networking Dinner
Event Venue
101 Innovation Dr, San Jose, CA 95134
Morning Breakout Session Details
Session Title |
Abstracts |
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Integrate AI into Your Existing FPGA Quickly | What is the FPGA AI Suite: Learn about the value of the FPGA AI Suite. How to Get Started: Learn how easy it is to get started by following installation instructions and prerequisites. Running Inference Tutorial: This tutorial explains the process and a few simple steps to run inference with performance and area estimation. |
Refine Custom Edge and Network AI Models onto FPGAs Easily | Real-World Applications: Discover real-world case studies highlighting the successful implementation of custom AI models using the FPGA AI Suite. CPU-FPGA Partitioning: We'll explore the nuanced process of CPU-FPGA partitioning and the critical role of memory access in boosting model performance. Optimize Performance: Learn how to exceed initial performance expectations using optimization and performance enhancement strategies. |
Scaling AI on SoC FPGAs | Versatile AI Deployment: Learn how to deploy and run a TinyML image classification model using the TensorFlow Lite Micro C++ library on both the Nios® V soft processor and the hardened Arm processor. Performance Insights: Discover the performance trade-offs between the Nios V and Arm processors within the FPGA environment, as well as the option to use FPGA AI Suite for further acceleration. Optimized Precision: Learn strategies for achieving high-precision AI on resource-constrained devices and understand how to optimize your TinyML applications for soft and hard processors in embedded systems. |
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Complete FPGA Design Development Faster | Design with the Newest Devices: Unlock the full potential of Agilex™ 5 and Agilex™ 7 FPGAs with Quartus® Prime Pro, providing developers with the tools needed to leverage the latest FPGA technology. Latest Software Innovations: FPGA development is simplified. Design Assistant, Design Netlist Infrastructure, Advanced Debug Capabilities, Multiple Compiler Options, and the Quartus Exploration Dashboard are key feature innovations streamlining the design process. Easy To Use Design Closure: Learn how these featured innovations streamline the design process and facilitate fast, more effective design closures. |
Accelerate Design Closure with Hardware and Software Innovations | Enhanced Speed and Efficiency: Learn how the high-performance fabric architecture, hardware and software co-design in Quartus, and core technology in the compiler deliver industry-leading performance and achieve fast timing closure. Optimized Power Consumption: Discover how power consumption is optimized for more reliable and efficient performance through the latest process nodes, integration of hardened IP and processor subsystems, and reduction in the need for soft logic. Advanced Analysis Tools: Learn about industry-leading timing, power and thermal analysis tools that streamline the design process, enhance performance, and reduce time to market. |
Unlocking Memory Potential | Industry Trends: Discover the latest trends shaping the memory industry and how Altera is innovating memory solutions. Device Selection: Learn how to pick the best devices for the highest bandwidth, best performance, and lowest power. Reducing Time to Market: Discover the powerful memory options that can speed up the project’s journey from concept to market. |
Afternoon Breakout Session Details
Session Title |
Abstracts |
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Debug Heterogenous Multi-Processors Efficiently | Reduce Time to Market: Learn how to improve productivity by reducing time to market using a single tool to debug applications running across heterogeneous architectures. Continuous Support: Learn about the capabilities of the Ashling RiscFree IDE for debugging an application that uses both the soft Nios V and the hardened Arm processors, which are supported by all Altera® SoC FPGAs, ensuring long-term compatibility and support. Industry-Standard Debug Environment: Discover how the environment aligns with the established workflows and practices developers are accustomed to in the embedded systems industry. |
Enable Asymmetric Processor Systems with Performance and Efficiency |
Operating Systems Compatibility: Learn about the operating systems available for Agilex 5 devices, such as Linux, and real-time operating systems (RTOS) like ZephyrRTOS, and how to leverage the hardware for optimal performance. Asymmetric Clustering Benefits: Explore the advantages of asymmetric clustering in computer systems, such as performance, cost reduction, increased reliability, and the ability to operate different nodes on various operating systems. New HPS Features in Agilex 5: Cache Stashing: Understanding the role of cache stashing in improving system performance by allowing certain data to be kept closer to the processor for fast access. USB 3.1 and I3C: A look at integrating modern interfaces like USB 3.1 Gen 1 and I3C for enhanced connectivity and data transfer capabilities. TSN EMAC: Discussing the Time-Sensitive Networking (TSN) Ethernet MAC (EMAC) support in Agilex 5, crucial for applications requiring precise timing and synchronization. |
FAQs
Frequently Asked Questions
Altera Innovators Day is a live, premier event for innovators by innovators.
Altera Innovators Day is for anyone interested in FPGAs — enthusiasts, hardware developers, decision-makers, or technical project leaders.
If you are an AI expert who wants to expand your knowledge, come and check out firsthand the benefits of FPGAi.
Whether you are from a well-established company or start-up, if you design electronic systems, this is a can’t-miss event.
This is a live, in-person event. A virtual replay will be available in the future.
Don't Forget to Register Your Interest!
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