1.1. External Memory Interfaces (EMIF) IP v3.0.0

External Memory Interfaces (EMIF) IP Release Notes: Agilex™ 3 FPGAs and SoCs

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ID 848079

Date 3/31/2025

Version 25.1

Public

Visible to Intel only — GUID: qql1740413940734

Ixiasoft

Table 1. v3.0.0 2025.03.31
Description	Impact
Verified in the Quartus® Prime software v25.1.	Provides external memory interface IP for Agilex™ 3 devices. The tables that follow summarize speed and feature support.

Note: This documentation is preliminary and subject to change.

Table 2. Agilex™ 3 C-Series Fabric EMIF/HPS EMIF IP Speed Support Summary
			Max Rate (Mbps/MHz)		-6				-7
Protocol	Category	Subcategory	-6	-7	S	C	T	H	S	C	T	H
LPDDR4	Memory Format	Both Fabric and HPS EMIF - Component	2133/1066 (1R)	2133/1066 (1R)	X	X	X¹		X	X	X¹
LPDDR4	Memory Format	Both Fabric and HPS EMIF - Component	2133/1066 (2R)	2133/1066 (2R)	X	X	X¹		X	X	X¹
Support level key: S = simulation support C = compilation support T = timing support H = hardware support X = supported feature. An empty table cell indicates that the feature is not currently supported. ¹ = Timing is currently preliminary. It will be necessary to recompile designs in future releases. Note: Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com.

Table 3. Agilex™ 3 C-Series Fabric EMIF IP Feature Support Summary
Protocol	Category	Sub-Category	Supported?	S	C	T
LPDDR4	Interface Width	1ch x32	X	X	X	X
		1ch x16	X	X	X	X
		2ch x16	X	X	X	X
	Controller	Hard Controller	X	X	X	X
	Design Example		X	X	X	X
	DBI	Read DBI	X	X	X	X
	DBI	Write DBI	X	X	X	X
	DM	DM pins	X	X	X	X
	Preamble	Read preamble settings	X	X	X	X
	Preamble	Write preamble settings
	Postamble	Read postamble settings	X	X	X	X
	Postamble	Write postamble settings	X	X	X	X
	Mainband access mode	Fabric Direct - user clock asychronous to PHY	X	X	X	X
	Mainband access mode	Fabric Direct - user clock sychronous to PHY	X	X	X	X
	ECC	In-line ECC	X	X	X	X
	Debug	EMIF Toolkit	X		X	X
	Simulators ¹	VCS
		VSC-MX	X	X
		Modelsim SE	X	X
		Xcelium	X	X
		Aldec
Support level key: S = simulation support C = compilation support T = timing support H = hardware support X = supported feature. ¹ = VHDL is not supported.

Table 4. Agilex™ 3 C-Series HPS EMIF IP Feature Support Summary
Protocol	Category	Sub-Category	Supported?	C	T
LPDDR4	Interface Width	1ch x32	X	X	X
		1ch x16	X	X	X
		2ch x16	X	X	X
	Controller	Hard controller	X	X	X
	Design Example
	DBI	Read DBI	X	X	X
	DBI	Write DBI	X	X	X
	DM	DM pins	X	X	X
	Preamble	Read preamble settings	X	X	X
	Preamble	Write preamble settings
	Postamble	Read postamble settings	X	X	X
	Postamble	Read postamble settings	X	X	X
	Mainband access mode	Direct path to HPS	X	X	X
	ECC	In-line ECC	X	X	X
	Debug	EMIF Toolkit
	Simulators ¹	VCS
		VCS-MX
		Modelsim SE
		Xcelium
		Aldec
Support level key: S = simulation support C = compilation support T = timing support H = hardware support X = supported feature. ¹ = VHDL is not supported.