Visible to Intel only — GUID: akq1724947516273
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1. About the Nios® V Processor Lockstep
2. Overview
3. Controlling the Nios® V Processor Lockstep
4. Programming Model
5. Signals, Interfaces, and Build Parameters
6. Using Nios® V Processor Lock Step
A. Document Revision History for the Nios® V Processor: Lockstep Implementation User Guide
B. Appendix
4.4.1. CPUs’ Reset Control Register - DCLSM_CPURC
4.4.2. DCLSM Basic Control Register - DCLSM_CTRL
4.4.3. DCLSM Blind Window Control Register - DCLSM_BWCR
4.4.4. All Alarms’ Prior Alarms’ Fault Injection Register - ERRCTRL_ALL_ALARMS_PRIOR_AFI
4.4.5. INTREQ Configuration Register - ERRCTRL_INTREQ_CONF
4.4.6. Timeout Deadline and Status Register - ERRCTRL_TIMEOUT
4.4.7. Timeout Acknowledgment Register - ERRCTRL_TIMEOUT_ACK
4.4.8. Enable Key fRSmartComp Control Register - ERRCTRL_ENABLE_KEY
4.4.9. Root Fault Injection Control register - ERRCTRL_ROOT_INJ
4.4.10. Alarm Fault Injection Control register - ERRCTRL_ALARM_INJ
4.4.11. Event Mask Configuration register - ERRCTRL_MASKA and ERRCTRL_MASKB
4.4.12. Alarm Routing Configuration register - ERRCTRL_ROUTA and ERRCTRL_ROUTB
4.4.13. Error Controller PGO LOG Reset Control register - ERRCTRL_PGOLOGRST
4.4.14. PGO0 and PGO4 Configuration registers - ERRCTRL_PGO0 and ERRCTRL_PGO4
4.4.15. FN_MODEIN Control Register - ERRCTRL_FNMODEIN
4.4.16. FN_MODEOUT register - ERRCTRL_FNMODEOUT
4.4.17. All Alarms After Fault Injection - ERRCTRL_FNGIALARMS
4.4.18. Error Controller Context Register - ERRCTRL_FNGICTXT4
4.4.19. CMP Mismatch CONTEXT Registers - ERRCTRL_FNGICMPCTXT0 … ERRCTRL_FNGICMPCTXT3
4.4.20. STATISTICS registers: ERRCTRL_FNGISTAT0 and ERRCTRL_FNGISTAT4
4.4.21. State register - ERRCTRL_FNPERIPHGI4
Visible to Intel only — GUID: akq1724947516273
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1.1. Nios® V Processor Lockstep Features
The Nios® V processor Lockstep mainly comprises the features listed in the following table.
Feature | Description |
---|---|
Self-checking Comparator |
|
Common Cause Failure Countermeasure | Time diversity by means of timing skew between the two Nios® V processor instances. |
Programmable Timers and Counters |
|
Error Controller Interface |
|
Configuration and Status Interface |
|
Built-in Hardware Fault Injector | Dummy faults injection facilities to ease chip-level hardware and software integration tests |
Supported processor | Nios® V/g processor |
Figure 2. Microarchitecture of Lockstep DCLS ArchitectureThis figure shows a conceptual view of the key features of the Lockstep DCLS architecture but does not represent the IP microarchitecture.
The fRSmartComp solution contains these interfaces:
- Configuration interface— Avalon® memory-mapped interface to configure and control the fRSmartComp solution.
- System interface—conduit representing the Lockstep alarm, reset, and mode signals.
- Extended Reset interface—reset interface for Extended Reset Control.