Nios® V Processor: Lockstep Implementation User Guide

ID 833274
Date 4/17/2025
Public

Visible to Intel only — GUID: bxb1725888118997

Ixiasoft

Document Table of Contents

2.1. Introduction

In the standard DCLS scheme, the outputs coming from the processors are compared by a comparator on a cycle-by-cycle basis. The two processors execute the same program flow. If the comparator detects a difference, it raises the alarm, signaling that a fault has been detected in one of the two processors without the opportunity to know in which of the two the fault has occurred.

Only one of the two processors (the Host) drives the system bus; the addresses and control information generated by the other processor (the Agent) does not affect the system.

Figure 3. Standard DCLS Architecture
Based on the standard DCLS architecture, the fRSmartComp is enhanced to handle an event of false positive faults along with timeout events. The following figure shows the two CPUs working in parallel with a timing skew between the two cores, implemented by means of flip-flop barriers. The timing skew provides time diversity, and hence a more robust implementation against common cause failures.
Figure 4. fRSmartComp DCLS Architecture with Time Diversity