GTS Transceiver Dual Simplex Interfaces User Guide

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ID 825853
Date 8/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Understanding and Planning Dual Simplex Interfaces 4. Implementing Dual Simplex Interfaces 5. Document Revision History for the GTS Transceiver Dual Simplex Interfaces User Guide
4. Implementing Dual Simplex Interfaces x
4.1. Generating the Simplex IP 4.2. Using the Dual Simplex Assignment Editor 4.3. Generating the Dual Simplex IP 4.4. Connecting the Dual Simplex IP 4.5. Verifying the Dual Simplex IP Implementation
1. Introduction
2. Overview
3. Understanding and Planning Dual Simplex Interfaces
4. Implementing Dual Simplex Interfaces
5. Document Revision History for the GTS Transceiver Dual Simplex Interfaces User Guide

4.4. Connecting the Dual Simplex IP

This section describes the steps to connect the previously generated dual simplex IP to your design.

The design requires the GTS Reset Sequencer Intel FPGA IP and GTS System PLL Clocks Intel FPGA IP to function correctly, therefore both IPs must be instantiated and connected to the DS IP.

To connect the dual simplex IP, follow these steps:
  1. The Quartus® Prime Pro Edition software displays the DS IP and the simplex IPs in the Project Navigator pane as shown in the following figure.
    Figure 19. Dual Simplex IP in the Project Navigator
    To view the top-level module of the DS IP, expand the DS_GROUP_0.qip file and click the DS_GROUP_0.sv SystemVerilog file as shown in the following figure.
    Figure 20. Dual Simplex IP Top-Level Module
    The Quartus® Prime Pro Edition software generates The DS IP port interface in the DS_GROUP_0.sv SystemVerilog file. The generated DS_GROUP_0.sv file retains all the ports as the simplex IPs and also merges the ports associated with the reset sequencer and system PLL (if used) as shown in the following figures.
    Figure 21.  DS_GROUP_0.sv RX Port Interface
    Figure 22.  DS_GROUP_0.sv TX Port Interface
    Figure 23.  DS_GROUP_0.sv Reset Sequencer and System PLL Ports Interface
  2. Next, instantiate the DS IP module in your top-level design file and make the necessary connections as per your design needs as shown in the following figure.
    Figure 24.  DS_GROUP_0.sv Instantiation
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