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1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Intel® FPGA IP Design Examples
3. Design Example: DisplayPort SST Parallel Loopback without PCR
4. Design Example: DisplayPort SST Parallel Loopback with AXIS Video Interface
5. Design Example: DisplayPort SST TX-Only Design
6. Design Example: DisplayPort SST RX-Only Design
7. Document Revision History for the DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs
1.5.1. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit
1.5.2. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular DevKit Connector with No FMC Mode
1.5.3. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular DevKit Connecter with Bitec Rev 8 Daughter Card
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1.5.1. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit
To compile and run a demonstration test on the hardware design example, follow these steps:
- Ensure hardware design example generation is complete.
- Launch the Quartus® Prime Pro Edition software and open <project>/quartus/agi_dp_demo.qpf.
- On the Processing menu, click Start Compilation.
- Confirm successful compilation by verifying that the IP generates the bitstream file (.sof) and meets the timing requirements.
- Connect the DisplayPort TX connector on the Bitec daughter card (Revision 8) to a DisplayPort sink device, such as a video analyzer or a PC monitor.
Note: The Premium Devkit transceiver reference clock (Si549) powers up at a frequency of 135MHz. To support DisplayPort, a 150MHz reference clock is necessary. When the design example software starts, it automatically reprograms the NIOS Application's reference clock.The following diagram shows the Premium Development Kit with the Bitec Rev 8 Daughter Card FMC installed:Figure 6. Premium Development Kit with the Bitec Rev 8 Daughter Card FMC Fitted
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