DisplayPort Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs

ID 823560
Date 12/20/2024
Public
Document Table of Contents

1.5.1. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit

To compile and run a demonstration test on the hardware design example, follow these steps:
  1. Ensure hardware design example generation is complete.
  2. Launch the Quartus® Prime Pro Edition software and open <project>/quartus/agi_dp_demo.qpf.
  3. On the Processing menu, click Start Compilation.
  4. Confirm successful compilation by verifying that the IP generates the bitstream file (.sof) and meets the timing requirements.
  5. Connect the DisplayPort TX connector on the Bitec daughter card (Revision 8) to a DisplayPort sink device, such as a video analyzer or a PC monitor.
    Note: The Premium Devkit transceiver reference clock (Si549) powers up at a frequency of 135MHz. To support DisplayPort, a 150MHz reference clock is necessary. When the design example software starts, it automatically reprograms the NIOS Application's reference clock.
    The following diagram shows the Premium Development Kit with the Bitec Rev 8 Daughter Card FMC installed:
    Figure 6. Premium Development Kit with the Bitec Rev 8 Daughter Card FMC Fitted