GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 823543
Date 5/30/2025
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Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS SDI II IP Design Example Quick Start Guide x
1.1. SDI II Design Example Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the SDI II Design Example in Hardware 1.5. SDI II Design Example Parameters
1.4. Compiling and Testing the SDI II Design Example in Hardware x
1.4.1. Testing in Hardware - Parallel or Serial Loopback
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. SDI II Design Example Signals 2.6. Design Limitations and Known Issues
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. SDI II Design Example Testbench Components 2.4.2. Test Description
1. GTS SDI II IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

1.3. Compiling and Simulating the Design

The GTS SDI II IP design example testbench simulates one channel serial loopback design with TX instance connected to an internal video pattern generator. The serial output from the TX instance connects to the RX instance in the testbench. The testbench also includes checkers and control mechanisms.

Figure 5. Simulating the Design Flow

To run example design simulation, follow these steps:

  1. Generate the necessary simulation setup files.
  2. Go to simulation folder.
  3. Go to the desired simulator folder and run the simulation script:
    1. ModelSim* SE or QuestaSim* FE: Got to mentor folder and type do mentor.do
    2. VCS* MX : Go to synopsys/vcsmx folder and type source vcsmx_sim.sh
    3. Xcelium* : Go to xcelium folder and type source xcelium_sim.sh
    4. Riviera-PRO* : Go to aldec folder and type do aldec.do
  4. A successful simulation ends with the following message:
Level Two Title