AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide
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Ixiasoft
Visible to Intel only — GUID: emi1718394726335
Ixiasoft
4.2. Design Examples

Parameter | Value | Default Value | Description |
---|---|---|---|
Simulation | Off | Off | When the Simulation box is checked, all necessary filesets for simulation are generated.
Note: Design example simulation is not supported in the current release.
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Synthesis | On/Off | On | When the Synthesis box is checked, all necessary filesets for synthesis are generated. When unchecked, only the Platform Designer system is generated. |
Generated file format | Verilog | Verilog | HDL format. |
Current development kit | None Intel Agilex™ 7 FPGA I-Series Development Kit (ES1 2x R-Tile & 1x F-Tile) Intel Agilex™ 7 FPGA I-Series Development Kit (ES2 2x R-Tile & 1x F-Tile) Intel Agilex™ 7 FPGA I-Series Development Kit (Production 2x R-Tile & 1x F-Tile) |
Agilex™ 7 FPGA I-Series Development Kit (ES1 2xR-Tile & 1xF-Tile) | Selects a target FPGA development kit board.
Note: If an FPGA development board is selected, the target device used for generation is the one that matches the device on the development kit board.
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Currently selected example design | AXI-MM BAM EP Memory AXI-MM Traffic Generator/Checker AXI-MM DMA AXI-S Device-side Packet Loopback |
AXI-S Device-side Packet Loopback | Selects a design example.
Note:
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Design example generation includes an AXI Streaming PCIe IP (intel_pcie_ss_axi). Hence, the Example Designs tab includes the AXI Streaming PCIe IP Parameter Editor. Some of the PCIe Interface parameters are automatically configured per the AXI MCDMA IP parameter values and greyed out.

Parameter | Value | Default Value | Description |
---|---|---|---|
PCIe Tile | R-Tile | R-Tile | Selects the supported Tile of the PCIe Interface.
Note: Only R-Tile is supported.
|
PCIe Profile | Basic Basic+ Virtual Virtual+ |
Basic | Selects functional features based on the profile like virtualization, additional interfaces, number of endpoints, etc. |
PCIe Mode | Gen5 1x16 Gen5 2x8 Gen4 1x16 Gen4 2x8 Gen3 1x16 Gen3 2x8 |
Gen5 1x16 | Selects a PCIe mode.
Note: For the 2x8 design example, you need to select 1x8 mode in the IP Settings > PCIe Mode, and then select 2x8 mode in the Example Designs > PCIe Mode setting.
|
Port Mode | Root Port Native Endpoint |
Native Endpoint | Selects a PCIe mode for the AXI Streaming PCIe IP.
Note: The mode value is passed from the AXI MCDMA IP Settings.
Note: The Root Port design example is not supported.
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Enable TLP-Bypass Mode | Off | Off | Enables the TLP-Bypass mode.
Note: TLP-Bypass mode is not supported in the current release.
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Enable PHY Reconfiguration | On / Off | Off | When on, this parameter creates an Avalon-MM slave interface that software can drive to update Transceiver reconfiguration registers. |
PLD Clock Frequency | Gen5/4 1x16, 2x8: 500/475/450/425/400 MHz Gen3 1x16, 2x8: 300/275/250 MHz |
500 MHz | Selects the PLD clock frequency. |
Enable SRIS Mode | On / Off | Off | Enables a separate reference clock with independent Spread Spectrum Clocking (SSC). |
Enable Debug Toolkit | Off | Off | Debug Toolkit is not supported. |
Enable PIPE Mode Simulation | On / Off | Off | When on, this parameter enables the PIPE mode simulation.
Note: Design example simulation is not supported in the current release.
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Refer to the AXI Streaming Intel® FPGA IP for PCI Express User Guide for other PCIe Interfaces' parameter descriptions. See Parameter Editor Parameters.