5.4.9. AXI4 Event Support
| Value | Event | Subevent | Description |
|---|---|---|---|
| 00h | COUNTER_IDLE | N/A | Counter Idle. |
| 01h | CLOCK_TICKS | N/A | Counts Clocks ticks after reset. |
| 02h | CLOCK_TICKS_AR2AR | N/A | Counts Clock ticks from the first Read command issued on the interface to the last/most recent command on the interface. It updates on every read command (ARREADY = 1 & ARVALID = 1) except the first. It increments by the number of cycles between the previous read command being issued to the last read command. |
| 03h | CLOCK_TICKS_R2R | N/A | Counts Clock ticks from the first read data issued on the interface to the last/most recent read data on the interface. It updates on every read data (RREADY = 1 & RVALID = 1) except the first. It increments by the number of cycles between the previous read data being issued to the last read data. |
| 04h | CLOCK_TICKS_AW2AW | N/A | Counts Clock ticks from the first write command issued on the interface to the last/most recent write command on the interface. It updates on every write command issued (AWREADY = 1 & AWVALID = 1) except the first. It increments by the number of cycles between the previous write command being issued to the last write command. |
| 05h | CLOCK_TICKS_W2W | N/A | Counts Clock ticks from the first write data issued on the interface to the last/most recent write data on the interface. It updates on every write data (WREADY = 1 & WVALID = 1) except the first. It increments by the number of cycles between the previous read data being issued to the last read data. |
| 06h | CLOCK_TICKS_B2B | N/A | Counts Clock ticks from the first write response issued on the interface to the last/most recent write response on the interface. It updates on every write response issued (BREADY = 1 & BVALID = 1) except the first. It increments by the number of cycles between the previous write response being issued to the last write response. |
| 07h | CLOCK_TICKS_AR2R | N/A | Counts Clock ticks from the first read command issued on the interface to the last/most recent read data on the interface. It updates on every read data (RREADY = 1 & RVALID = 1) past the first read command detected. It increments by the number of cycles between the first read command issued to the first read response on its first increment. Every increment past that is the number of cycles between the previous read data being issued to the last read data. |
| 08h | CLOCK_TICKS_AWW2B | N/A | Counts Clock ticks from the first write command/data issued on the interface to the last/most recent write response on the interface. It updates on every write response issued (BREADY = 1 & BVALID = 1) past the first write command/data detected. It increments by the number of cycles between the write response to the write command or data it detected first, on its first increment. For all increments past the first it increments by the number of cycles between the previous write response being issued to the last write response. |
| 09h | CLOCK_TICKS_ARAWW2RB | N/A | Counts Clock ticks from the first read command or write command/data issued on the interface to the last write response or read data on the interface. It updates on every write response issued past the first read command or write command/data detected. It increments by the number of cycles between the write response to the write command or data it detected first, on its first increment. For all increments past the first it increments by the number of cycles between the previous write response or read data being issued to the last write response or read data. |
| 0Ah - 0Fh | RESERVED | N/A | Reserved |
| 10h | READ_OCCUPANCY | 0: ARVALID=1 & ARREADY=1 (number of transactions) 1: ARVALID=0 (idle cycles) 2: ARVALID=1 & ARREADY=0 (backpressure cycles) 3: RVALID=1 & RREADY=1 (number of transactions) 4: RVALID=0 (idle cycles) 5: RVALID=1 & RREADY=0 (backpressure cycles) |
Counts cycles in which combinations of signals are active on the read address and read data channels. If no subevents are set the counter will increment if any subevent has its conditions met. |
| 11h | READ_CMD_LENGTH | N/A | The number of data transfers performed on read transactions requested by the Read Command channel. Increments on a read transaction (ARVALID=1 & ARREADY=1) by ARLEN+1. |
| 12h | READ_CMD_BYTES | N/A | The number of bytes transferred on read transactions. Increments on a read transaction (ARVALID=1 & ARREADY=1) by (ARLEN+1) <<ARSIZE. |
| 13h | TOTAL_READ_LATENCY | N/A | Total Read Latency, cumulative count. Read latency is measured from the clock cycle at which a read command transaction is accepted on the AXI Read Command interface (ARVALID & ARREADY) to the clock cycle where the corresponding last Read Data Valid (RVALID & RLAST & RREADY) signal is asserted on the AXI read response interface. |
| 14h - 17h | RESERVED | N/A | Reserved |
| 18h | WRITE_OCCUPANCY | 0: AWVALID=1 & AWREADY=1 (number of transactions) 1: AWVALID=0 (idle cycles) 2: AWVALID=1 & AWREADY=0 (backpressure cycles) 3: WVALID=1 & WREADY=1 (number of transactions) 4: WVALID=0 (idle cycles) 5: WVALID=1 & WREADY=0 (backpressure cycles) |
Counts cycles in which combinations of signals are active on the Write address and write data channels. If no subevents are set the counter will increment if any subevent has its conditions met. |
| 19h | RESPONSE_OCCUPANCY | 0: BVALID=1 & BREADY=1 (number of transactions) 1: BVALID=0 (idle cycles) 2: BVALID=1 & BREADY=0 (backpressure cycles) |
Counts cycles in which combinations of signals are active on the Write response channel. If no subevents are set the counter will increment if any subevent has its conditions met. |
| 1Ah | WRITE_CMD_LENGTH | N/A | The number of data transfers performed on write transactions requested by the Write Command channel. Increments on a write transaction (AWVALID=1 & AWREADY=1) by AWLEN+1. |
| 1Bh | WRITE_CMD_BYTES | N/A | The number of bytes transferred on write transactions. Increments on a write transaction (AWVALID=1 & AWREADY=1) by (AWLEN+1) <<AWSIZE. |
| 1Ch | TOTAL_WRITE_LATENCY | N/A | Total Write Latency, cumulative count. Write latency is measured from the clock cycle at which a write command is accepted the on AXI write command interface (AWVALID & AWREADY) to the clock cycle where the corresponding Write Response Valid (BVALID & BREADY) signal is asserted on the AXI write response interface. Is ID agnostic. |
| 1Dh - EFh | RESERVED | N/A | Reserved |
| F0h | CLOCK_TICKS_OVFL | 0: AR2AR 1: R2R 2: AW2AW 3: W2W 4: B2B 5: AR2R 6: AWW2B 7: ARAWW2RB |
Used for checking if X2X event internal counters have overflowed. Do NOT need to be set with events to trigger rather can be checked once metrics are read by switching the counter to this event. If the internal counter has overflowed at any point during traffic & the requisite event was valid afterward then the counter will increment as CLOCK_TICKS. This will act as a binary check. |
| F1h - FEh | RESERVED | N/A | Reserved |
| FFh | PMON_LAT_DEBUG_EVENT | 4:Read Latency outstanding transactions overflow 5:Write Latency outstanding transactions overflow |
Used for debugging PMON. Subevents 4 and 5 are for read and write latency, if there is an increment overflow based on the number of outstanding transactions. |