GTS Ethernet Intel® FPGA Hard IP User Guide

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ID 817676
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. GTS Ethernet Intel® FPGA Hard IP Parameters 4. Integrate GTS Ethernet Intel® FPGA Hard IP to the User Application 5. Functional Description 6. Configuration Registers 7. Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
1. Overview x
1.1. Agilex™ 5 Ethernet Portfolio and Target Applications 1.2. Agilex™ 5 Ethernet Hard IP Features 1.3. High-Level Functional Overview 1.4. GTS Ethernet Intel® FPGA Hard IP Design Flow
1.2. Agilex™ 5 Ethernet Hard IP Features x
1.2.1. Device Family Support 1.2.2. Device Speed Grade Support 1.2.3. Resource Utilization 1.2.4. Round-Trip Latency 1.2.5. Release Information
2. Getting Started x
2.1. Installing and Licensing GTS Ethernet Intel® FPGA Hard IP Cores 2.2. Generate HDL for Synthesis and Simulation 2.3. Generated File Structure
4. Integrate GTS Ethernet Intel® FPGA Hard IP to the User Application x
4.1. Clocks 4.2. Resets 4.3. MAC Client Interface – Avalon® Streaming Interface 4.4. PCS Client Interface – MII PCS Only 4.5. PCS66 Client Interface – FlexE and OTN 4.6. Connect the Status Interface 4.7. Ethernet Hard IP Reconfiguration Interface 4.8. Precision Time Protocol Interface
4.1. Clocks x
4.1.1. MAC Synchronous Clock Connections to Single Instance 4.1.2. MAC Synchronous Clock Connections to Multiple Instances 4.1.3. Clock Connections to MAC Asynchronous Operation 4.1.4. Clock Connections in PTP-Based Synchronous Operation 4.1.5. Clock Connections in Synchronous Ethernet Operation (Sync-E) 4.1.6. I/O PLL as System PLL
4.2. Resets x
4.2.1. Reset Signals 4.2.2. Reset Sequence 4.2.3. Power Up Reset Sequence 4.2.4. TX Reset Entry Sequence 4.2.5. TX Reset Exit Sequence 4.2.6. RX Reset Entry Sequence 4.2.7. RX Reset Exit Sequence 4.2.8. Auto Recovery Reset Sequence 4.2.9. GTS Reset Sequencer Intel® FPGA IP
4.2.9. GTS Reset Sequencer Intel® FPGA IP x
4.2.9.1. Requirements and Considerations for GTS Reset Sequencer Intel® FPGA IP
4.3. MAC Client Interface – Avalon® Streaming Interface x
4.3.1. TX MAC Avalon Streaming Client Interface 4.3.2. RX MAC Avalon Streaming Client Interface 4.3.3. MAC Flow Control Interface
4.3.1. TX MAC Avalon Streaming Client Interface x
4.3.1.1. TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough 4.3.1.2. TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough 4.3.1.3. Control Source Address, PAD, and CRC Insertion 4.3.1.4. Assert the i_tx_error to Invalidate a Packet
4.3.2. RX MAC Avalon Streaming Client Interface x
4.3.2.1. RX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough 4.3.2.2. Enable Preamble Passthrough and RX CRC Forwarding 4.3.2.3. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
4.3.3. MAC Flow Control Interface x
4.3.3.1. TX PAUSE and TX PFC Ports 4.3.3.2. Receiving PAUSE and PFC Frames
4.4. PCS Client Interface – MII PCS Only x
4.4.1. PCS Mode TX Interface 4.4.2. PCS Mode RX Interface
4.5. PCS66 Client Interface – FlexE and OTN x
4.5.1. FlexE and OTN Mode TX Interface 4.5.2. FlexE and OTN Mode RX Interface
4.6. Connect the Status Interface x
4.6.1. Status Interface
4.8. Precision Time Protocol Interface x
4.8.1. Time-of-Day Interface 4.8.2. TX 2-Step Timestamp Interface 4.8.3. TX 1-Step Timestamp Interface 4.8.4. RX Timestamp Interface 4.8.5. PTP Status Interface
4.8.3. TX 1-Step Timestamp Interface x
4.8.3.1. PTP Field Offset for 1-Step Operation
5. Functional Description x
5.1. Datapath Description 5.2. GTS Ethernet Intel® FPGA Hard IP MAC 5.3. PCS, OTN, and FlexE Modes 5.4. Precision Time Protocol Interface
5.2. GTS Ethernet Intel® FPGA Hard IP MAC x
5.2.1. MAC TX Datapath 5.2.2. MAC RX Datapath 5.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 5.2.4. Link Fault Signaling 5.2.5. Order of Ethernet Transmission:
5.2.1. MAC TX Datapath x
5.2.1.1. TX Preamble, Start, and SFD Insertion 5.2.1.2. Source Address Insertion 5.2.1.3. Length/Type Field Processing 5.2.1.4. Frame Padding 5.2.1.5. Frame Check Sequence (CRC-32) Insertion 5.2.1.6. Inter-Packet Gap Generation and Insertion
5.2.2. MAC RX Datapath x
5.2.2.1. RX Preamble Processing 5.2.2.2. RX Strict SFD Checking 5.2.2.3. RX FCS Checking 5.2.2.4. RX Malformed Packet Handling 5.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 5.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 5.2.2.7. Inter-Packet Gap
5.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
5.2.3.1. Conditions Triggering XOFF Frame Transmission 5.2.3.2. Conditions Triggering XON Frame Transmission 5.2.3.3. Pause Control and Generation Interface 5.2.3.4. Pause Control Frame Filtering
5.3. PCS, OTN, and FlexE Modes x
5.3.1. PCS Mode 5.3.2. OTN Mode 5.3.3. FlexE Mode
5.4. Precision Time Protocol Interface x
5.4.1. Features 5.4.2. PTP User Flow 5.4.3. UI Adjustment 5.4.4. Reference Time Interval 5.4.5. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware)
5.4.2. PTP User Flow x
5.4.2.1. PTP TX User Flow 5.4.2.2. PTP RX User Flow
5.4.3. UI Adjustment x
5.4.3.1. TX UI Adjustment 5.4.3.2. RX UI Adjustment
6. Configuration Registers x
6.1. Ethernet Avalon® Memory-Mapped Interface Address Space 6.2. GTS Ethernet Intel® FPGA Hard IP Core CSRs 6.3. Transceiver Avalon® Memory-Mapped Interface Address Space
1. Overview
2. Getting Started
3. GTS Ethernet Intel® FPGA Hard IP Parameters
4. Integrate GTS Ethernet Intel® FPGA Hard IP to the User Application
5. Functional Description
6. Configuration Registers
7. Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide

4.1. Clocks

This section describes the required clock connections and clock signals for various GTS System PLL Clock Intel FPGA IP core variations.

The following image shows the clock connection for Synchronous Adapter Modes.

Figure 8. Conceptual Overview of General IP Clock Connection for Synchronous Adapter Modes
The GTS Ethernet Intel® FPGA Hard IP requires two clock inputs:
  • i_clk_ref PMA reference clock
  • i_clk_sys datapath clock.

    The output of the GTS System PLL Clocks Intel® FPGA IP drives the i_clk_sys datapath clock.

    The i_refclk clock for the System PLL IP can be sourced from either local, regional, or HVIO reference clock pin. Furthermore, the GTS Ethernet Intel® FPGA Hard IP can receive its input reference clock from the IO PLL in HVIO bank.

Either local or regional reference clock pins can be used to drive the i_clk_ref PMA reference clock. The local reference clock pin is bidirectional, except when there is a single GTS transceiver bank on an FPGA side, where it functions solely as an input reference clock pin. This bidirectional pin can be configured as an output for the Clock Data Recovery (CDR) recovered clock o_cdr_divclk from any of the four channels within the GTS transceiver bank. The device with single GTS transceiver bank has a dedicated output pin for the CDR recovered clock. For more information on the GTS System PLL Intel® FPGA IP, refer to the GTS Transceiver PHY User Guide.

The following figure shows all of the available clock inputs, clock outputs, and status signals when you generate the Ethernet Hard IP variant.
Figure 9. GTS Ethernet Intel® FPGA Hard IP Clock Signals

The following table describes necessary input and output clocks with required clock frequencies, and the clock-related status signals.

Table 14.  Clock Signals
Name Description
Clock Inputs
i_clk_tx

TX datapath clock

Drives the active TX Interface for the channel.

Clock source:

  • The o_clk_pll clock applies to MAC synchronous operation mode when Enable asynchronous adapter clocks parameter is disabled.
  • In MAC asynchronous operation, drive this clock according to the frequency specified in Minimum Clock Rates for MAC Asynchronous Operation.
i_clk_rx

RX datapath clock

Drives the active RX Interface for the channel.

Clock source:
  • The o_clk_pll clock applies to MAC synchronous operation mode when Enable asynchronous adapter clocks parameter is disabled.
  • In MAC asynchronous operation, drive this clock according to the frequency specified in Minimum Clock Rates for MAC Asynchronous Operation.
i_clk_sys

Ethernet system clock

Ethernet System Clock from GTS System PLL Clocks Intel® FPGA IP .
Note:
  • The i_clk_sys is a virtual signal. In simulation, the signal appears as 0.
  • For 10GE, use 322.265625 MHz.
i_clk_ref_p

Reference Clock for TX PLL per Channel

For 10GE, use 322.265625 MHz.

i_reconfig_clk

Avalon memory-mapped interface reconfiguration clock

Avalon® memory-mapped interface uses this clock to access control status registers (CSRs). This clock supports 100 to 125 MHz frequency.

i_clk_pll

PTP-related datapath clock

PTP internal datapath clock. Refer Clock Connections in PTP-Based Synchronous Operation for clocking requirements.

Clock Outputs
o_clk_pll

System PLL clock

Clock derived from the GTS Ethernet Intel® FPGA Hard IP .

The frequency is the system PLL frequency divided by 2 (e.g., 806 MHz system PLL would result in a 403 MHz o_clk_pll)

  • 161.1328125 MHz Minimum EHIP system clock for 10GE channels
o_clk_tx_div This clock is derived from TX PLL. The frequency data rate is divided by 66.

156.25 MHz (+/- 100 ppm) TX PLL rate is divided by 66 for 10GE channels.
o_clk_rec_div64

This recovered clock is derived from the CDR. The frequency data rate is divided by 64.

161.1328125 MHz (+/- 100 ppm) data rate is divided by 64 for 10GE channels.

o_clk_rec_div

This recovered clock derived from the CDR. The frequency data rate is divided by 66.

156.25 MHz (+/- 100 ppm) for 10GE channels.

o_cdr_divclk

Dedicated CDR divided clock output from PMA over the Local Reference Clock pins or dedicated CDR clock output pins. Refer Figure 8

This clock is available when Enabled Dedicated CDR Clock Output is enabled in the IP parameter editor.

i_pma_cu_clk

PMA Control Unit Clock

Connect this clock to o_pma_cu_clk output of the GTS Reset Sequencer Intel® FPGA IP. Refer input and output signals of the Figure 25 Intel® FPGA IP diagram for more details.

Clock Status
i_syspll_lock Indicates that Sys PLL is locked.
o_cdr_lock

This signal indicates that the recovered clocks are locked to data.

Do not use o_clk_rec_div64 or o_clk_rec_div until o_cdr_lock is high.

o_sys_pll_locked Indicates o_clk_pll is good to use.
o_tx_pll_locked

TX serdes PLLs are locked.

Do not use o_clk_pll or o_clk_tx_div until o_tx_pll_locked is high.


Section Content
MAC Synchronous Clock Connections to Single Instance
MAC Synchronous Clock Connections to Multiple Instances
Clock Connections to MAC Asynchronous Operation
Clock Connections in PTP-Based Synchronous Operation
Clock Connections in Synchronous Ethernet Operation (Sync-E)
I/O PLL as System PLL

Related Information
Level Two Title