External Memory Interfaces (EMIF) IP Release Notes: Agilex™ 5 FPGAs and SoCs

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ID 817396
Date 11/18/2024
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1. External Memory Interfaces (EMIF) IP Release Notes: Agilex™ 5 FPGAs and SoCs
1. External Memory Interfaces (EMIF) IP Release Notes: Agilex™ 5 FPGAs and SoCs x
1.1. External Memory Interfaces (EMIF) IP v1.0.0 1.2. External Memory Interfaces (EMIF) IP v6.2.0 1.3. External Memory Interfaces (EMIF) IP v6.1.0
1. External Memory Interfaces (EMIF) IP Release Notes: Agilex™ 5 FPGAs and SoCs

1.1. External Memory Interfaces (EMIF) IP v1.0.0

Table 1.  v1.0.0 2024.11.18
Description Impact
External Memory Interface IP for Agilex™ 5 devices now divided into individual IPs based on memory protocol and format. This release provides separate IPs for DDR4 Component, DDR4 DIMM, DDR5 Component, DDR5 DIMM, LPDDR4, and LPDDR5. Each IP is now labeled as version 1.0.0.
Verified in the Quartus® Prime software v24.3. Provides external memory interface IP for Agilex™ 5 devices. The tables that follow summarize speed and feature support.
Note: This documentation is preliminary and subject to change.
Table 2.   Agilex™ 5 E-Series Device Group A Fabric EMIF/HPS EMIF IP Speed Support Summary
      Max Rate (Mbps/MHz)   -1V -2V -3V
Protocol Category Subcategory -1V -2V -3V Support Detail S C T H S C T H S C T H
DDR4 Memory Format Both Fabric and HPS EMIF - Component 2667/1333 (1R) 2667/1333 (1R) 2133/1066 (1R)   X X X 1   X X X 1   X X X 1  
2667/1333 (2R) 2667/1333 (2R) 2133/1066 (2R)   X X X 1   X X X 1   X X X 1  
DDR5 Memory Format Both Fabric and HPS EMIF - Component 3600/1800 (1R) 3600/1800 (1R) 3200/1600 (1R)   X X X 1   X X X 1   X X X 1  
3600/1800 (2R) 3600/1800 (2R) 3200/1600 (2R)   X X X 1   X X X 1   X X X 1  
LPDDR4 Memory Format Both Fabric and HPS EMIF - Component 3733/1866 (1R) 3733/1866 (1R) 3200/1600 (1R)   X X X 1   X X X 1   X X X 1  
3733/1866 (2R) 3733/1866 (2R) 3200/1600 (2R)   X X X 1   X X X 1   X X X 1  
LPDDR5 Memory Format Both Fabric and HPS EMIF - Component 3733/1866 (1R) 3733/1866 (1R) 3200/1600 (1R)   X X X 1   X X X 1   X X X 1  
3733/1866 (2R) 3733/1866 (2R) 3200/1600 (2R)   X X X 1   X X X 1   X X X 1  
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • An empty table cell indicates that the feature is not currently supported.
  • 1 = Timing is currently preliminary. It will be necessary to recompile designs in future releases.

Note: Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com.
Table 3.   Agilex™ 5 E-Series Device Group A Fabric EMIF IP Feature Support Summary
Protocol Category Sub-Category Supported? S C T H
DDR4 Interface Width 16, 16+ECC X X X X  
32, 32+ ECC X X X X  
Controller Hard controller X X X X  
3DS 3DS          
Design Example   X X X X  
DBI Read DBI X X X X  
Write DBI X X X X  
DM DM pins X X X X  
Preamble Read preamble settings X X X X  
Write preamble settings X X X X  
Mainband access mode Fabric Direct - User Clock Asynchronous to PHY X X X X  
Fabric Direct - User Clock Synchronous to PHY X X X X  
ECC Out-of-band ECC X X X X  
Debug EMIF Toolkit X X X X  
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX X X      
Modelsim SE X X      
Xcelium X X      
Aldec          
DDR5 Interface Width 16, 16+ECC X X X X  
32, 32+ ECC X X X X  
Controller Hard controller X X X X  
Design Example   X X X X  
DM DM pins X X X X  
Preamble Read preamble settings X X X X  
Write preamble settings X X X X  
Postamble Read postamble settings X X X X  
Write postamble settings X X X X  
Mainband access mode Fabric Direct - User Clock Asynchronous to PHY X X X X  
Fabric Direct - User Clock Synchronous to PHY X X X X  
ECC Out-of-band ECC X X X X  
Debug EMIF Toolkit X X X X  
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX X X      
Modelsim SE X X      
Xcelium X X      
Aldec          
LPDDR4 Interface Width 1ch x32 X X X X  
1ch x16 X X X X  
2ch x16 X X X X  
4ch x16 X X X X  
Controller Hard controller X X X X  
Design Example   X X X X  
DBI Read DBI X X X X  
Write DBI X X X X  
DM DM pins X X X X  
Preamble Read preamble settings X X X X  
Write preamble settings          
Postamble Read postamble settings X X X X  
Read postamble settings X X X X  
Mainband access mode Fabric Direct - User Clock Asynchronous to PHY X X X X  
Fabric Direct - User Clock Synchronous to PHY X X X X  
ECC In-line ECC X X X X  
Debug EMIF Toolkit X X X X  
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX X X      
Modelsim SE X X      
Xcelium X X      
Aldec          
LPDDR5 Interface Width 1ch x32 X X X X  
1ch x16 X X X X  
2ch x16 X X X X  
4ch x16 X X X X  
Controller Hard controller X X X X  
Design Example   X X X X  
DBI Read DBI X X X X  
Write DBI X X X X  
DM DM pins X X X X  
Preamble Read preamble settings X X X X  
Write preamble settings          
Postamble Read postamble settings X X X X  
Write postamble settings X X X X  
Mainband access mode Fabric Direct - User Clock Asynchronous to PHY X X X X  
Fabric Direct - User Clock Synchronous to PHY X X X X  
ECC In-line ECC X X X X  
WR Link ECC X X X X  
RD Link ECC X X X X  
Debug EMIF Toolkit X X X X  
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX X X      
Modelsim SE X X      
Xcelium X X      
Aldec          
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 1 = VHDL is not supported.
Table 4.   Agilex™ 5 E-Series Device Group A HPS EMIF IP Feature Support Summary
Protocol Category Sub-Category Supported? S C T H
DDR4 Interface Width 16, 16+ECC X   X X  
32, 32+ ECC X   X X  
Controller Hard controller X   X X  
3DS 3DS          
Design Example            
DBI Read DBI X   X X  
Write DBI X   X X  
DM DM pins X   X X  
Preamble Read preamble settings X   X X  
Write preamble settings X   X X  
Mainband Access mode Direct path to HPS X   X X  
ECC Out-of-band ECC X   X X  
Debug EMIF Toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX          
Modelsim SE          
Xcelium          
Aldec          
DDR5 Interface Width 16, 16+ECC X   X X  
32, 32+ ECC X   X X  
Controller Hard controller X   X X  
Design Example            
DM DM pins X   X X  
Preamble Read preamble settings X   X X  
Write preamble settings X   X X  
Postamble Read postamble settings X   X X  
Write postamble settings X   X X  
Mainband access mode Direct path to HPS X   X X  
ECC Out-of-band ECC X   X X  
Debug EMIF Toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX          
Modelsim SE          
Xcelium          
Aldec          
LPDDR4 Interface Width 1ch x32 X   X X  
1ch x16 X   X X  
2ch x16 X   X X  
4ch x16 X   X X  
Controller Hard controller X   X X  
Design Example            
DBI Read DBI X   X X  
Write DBI X   X X  
DM DM pins X   X X  
Preamble Read preamble settings X   X X  
Write preamble settings          
Postamble Read postamble settings X   X X  
Read postamble settings X   X X  
Mainband access mode Direct path to HPS X   X X  
ECC In-line ECC X   X X  
Debug EMIF Toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX          
Modelsim SE          
Xcelium          
Aldec          
LPDDR5 Interface Width 1ch x32 X   X X  
1ch x16 X   X X  
2ch x16 X   X X  
4ch x16 X   X X  
Controller Hard controller X   X X  
Design Example            
DBI Read DBI X   X X  
Write DBI X   X X  
DM DM pins X   X X  
Preamble Read preamble settings X   X X  
Write preamble settings          
Postamble Read postamble settings X   X X  
Write postamble settings X   X X  
Mainband access mode Direct path to HPS X   X X  
ECC In-line ECC X   X X  
WR Link ECC X   X X  
RD Link ECC X   X X  
Debug EMIF Toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX          
Modelsim SE          
Xcelium          
Aldec          
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 1 = VHDL is not supported.
Table 5.   Agilex™ 5 E-Series Device Group B (ES0) Fabric EMIF / HPS EMIF IP Speed Support Summary 2
      Max Rate (Mbps/MHz)   -4 -5 -6
Protocol Category Subcategory -4 -5 -6 Support Detail S C T H S C T H S C T H
DDR4 Memory Format Fabric EMIF - Component 2400/1200 (1R) 1866/933 (1R) 1600/800 (1R)   X X X 1 X X X X 1 X X X X 1 X
2400/1200 (2R) 1866/933 (2R) 1600/800 (2R)   X X X 1 X X X X 1 X X X X 1 X
HPS EMIF - Component 2133/1066 (1R) 1866/933 (1R) 1600/800 (1R)   X X X 1 X X X X 1 X X X X 1 X
2133/1066 (2R) 1866/933 (2R) 1600/800 (2R)   X X X 1 X X X X 1 X X X X 1 X
LPDDR4 Memory Format Both Fabric and HPS EMIF - Component 2667/1333 (1R) 2133/1066 (1R) 1600/800 (1R)   X X X 1 X X X X 1 X X X X 1 X
2667/1333 (2R) 2133/1066 (2R) 1600/800 (2R)   X X X 1 X X X X 1 X X X X 1 X
LPDDR5 Memory Format Both Fabric and HPS EMIF - Component 2133/1066 (1R) 2133/1066 (1R) 1600/800 (1R)   X X X 1 X X X X 1 X X X X 1 X
2133/1066 (2R) 2133/1066 (2R) 1600/800 (2R)   X X X 1 X X X X 1 X X X X 1 X
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • An empty table cell indicates that the feature is not currently supported.
  • 1 = Timing is currently preliminary. It will be necessary to recompile designs in future releases..
  • 2 = Applicable to the following ES0 OPNs in the Quartus Prime Software version 24.3: A5EC065BB23AEXSR0, A5EC065BB32AEXSR0, A5ED065BB23AEXSR0 and A5ED065BB32AEXSR0.

Note: Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com.
Table 6.   Agilex™ 5 E-Series Device Group B (ES0) Fabric EMIF IP Feature Support Summary 1
Protocol Category Sub-Category Supported? S C T H
DDR4 Interface Width 16, 16+ECC X X X X X
32, 32+ECC X X X X X
Controller Hard controller X X X X X
3DS 3DS          
Design Example   X X X X X
DBI Read DBI          
Write DBI X X X X X
DM DM pins X X X X X
Preamble Read preamble settings X X X X X
Write preamble settings X X X X X
Mainband access mode Fabric Direct - User Clock Asynchronous to PHY X X X X X
Fabric Direct - User Clock Synchronous to PHY X X X X X
ECC Out-of-band ECC X X X X X
Debug EMIF Toolkit X X X X X
Simulation Abstract PHY          
Simulators 2 VCS          
VCS-MX X X      
ModelSim SE X X      
Xcelium X X      
Aldec          
LPDDR4 Interface Width 1ch x32 X X X X X
1ch x16 X X X X X
2ch x16 X X X X X
4ch x16 X X X X X
Controller Hard controller X X X X X
Design Example   X X X X X
DBI Read DBI          
Write DBI X X X X X
DM DM pins X X X X X
Preamble Read preamble settings          
Write preamble settings          
Postamble Read postamble settings X X X X X
Write postamble settings X X X X X
Mainband access mode Fabric Direct - User Clock Asynchronous to PHY X X X X X
Fabric Direct - User Clock Synchronous to PHY X X X X X
ECC In-line ECC X X X X X
Debug EMIF toolkit X X X X X
Simulation Abstract PHY          
Simulators 2 VCS          
VCS-MX X X      
ModelSim SE X X      
Xcelium X X      
Aldec          
LPDDR5 Interface Width 1ch x32 X X X X X
1ch x16 X X X X X
2ch x16 X X X X X
4ch x16 X X X X X
Controller Hard controller X X X X X
Design Example   X X X X X
DBI Read DBI          
Write DBI X X X X X
DM DM pins X X X X X
Preamble Read preamble settings X X X X X
Write preamble settings          
Postamble Read postamble settings X X X X X
Write postamble settings X X X X X
Mainband access mode Fabric Direct - User Clock Asynchronous to PHY X X X X X
Fabric Direct - User Clock Synchronous to PHY X X X X X
ECC In-line ECC X X X X X
WR Link ECC          
RD Link ECC          
Debug EMIF toolkit X X X X X
Simulation Abstract PHY          
Simulators 2 VCS          
VCS-MX X X      
ModelSim SE X X      
Xcelium X X      
Aldec          
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 1 = Applicable to these OPNs: A5EC065BB23AEXSR0, A5EC065BB32AEXSR0, A5ED065BB23AEXSR0 and A5ED065BB32AEXSR0.
  • 2 = VHDL is not supported.
Table 7.   Agilex™ 5 E-Series Device Group B (ES0) HPS EMIF IP Feature Support Summary 1
Protocol Category Sub-Category Supported? S C T H
DDR4 Interface Width 16, 16+ECC X   X X X
32, 32+ECC X   X X X
Controller Hard controller X   X X X
3DS 3DS          
Design Example            
DBI Read DBI          
Write DBI X   X X X
DM DM pins X   X X X
Preamble Read preamble settings X   X X X
Write preamble settings X   X X X
Mainband access mode Hard path to HPS X   X X X
ECC Out-of-band ECC X   X X X
Debug EMIF Toolkit          
Simulation Abstract PHY          
Simulators 2 VCS          
VCS-MX          
ModelSim SE          
Xcelium          
Aldec          
LPDDR4 Interface Width 1ch x32 X   X X X
1ch x16 X   X X X
2ch x16 X   X X X
4ch x16 X   X X X
Controller Hard controller X   X X X
Design Example            
DBI Read DBI          
Write DBI X   X X X
DM DM pins X   X X X
Preamble Read preamble settings          
Write preamble settings          
Postamble Read postamble settings X   X X X
Write postamble settings X   X X X
Mainband access mode Hard path to HPS X   X X X
ECC In-line ECC X   X X X
Debug EMIF toolkit          
Simulation Abstract PHY          
Simulators 2 VCS          
VCS-MX          
ModelSim SE          
Xcelium          
Aldec          
LPDDR5 Interface Width 1ch x32 X   X X X
1ch x16 X   X X X
2ch x16 X   X X X
4ch x16 X   X X X
Controller Hard controller X   X X X
Design Example            
DBI Read DBI          
Write DBI X   X X X
DM DM pins X   X X X
Preamble Read preamble settings X   X X X
Write preamble settings          
Postamble Read postamble settings X   X X X
Write postamble settings X   X X X
Mainband access mode Hard path to HPS X   X X X
ECC In-line ECC X   X X X
WR Link ECC          
RD Link ECC          
Debug EMIF toolkit          
Simulation Abstract PHY          
Simulators 2 VCS          
VCS-MX          
ModelSim SE          
Xcelium          
Aldec          
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 1 = Applicable to these OPNs: A5ED065BB23AEXSR0 and A5ED065BB32AEXSR0.
  • 2 = VHDL is not supported.

Table 8.   Agilex™ 5 E-Series Device Group B Fabric EMIF/HPS EMIF IP Speed Support Summary 2
      Max Rate (Mbps/MHz)   -4 -5 -6
Protocol Category Subcategory -4 -5 -6 Support Detail S C T H S C T H S C T H
DDR4 Memory Format Fabric EMIF - Component 2400/1200 (1R) 2133/1066 (1R) 1866/933 (1R)   X X X 1 X X X X 1 X X X X 1 X
2400/1200 (2R) 2133/1066 (2R) 1866/933 (2R)   X X X 1 X X X X 1 X X X X 1 X
HPS EMIF - Component 2133/1066 (1R) 1866/933 (1R) 1600/800 (1R)   X X X 1 X X X X 1 X X X X 1 X
2133/1066 (2R) 1866/933 (2R) 1600/800 (2R)   X X X 1 X X X X 1 X X X X 1 X
LPDDR4 Memory Format Both Fabric and HPS EMIF - Component 2667/1333 (1R) 2667/1333 (1R) 2133/1066 (1R)   X X X 1 X X X X 1 X X X X 1 X
2667/1333 (2R) 2667/1333 (2R) 2133/1066 (2R)   X X X 1 X X X X 1 X X X X 1 X
LPDDR5 Memory Format Both Fabric and HPS EMIF - Component 2133/1066 (1R) 2133/1066 (1R) 1600/800 (1R)   X X X 1 X X X X 1 X X X X 1 X
2133/1066 (2R) 2133/1066 (2R) 1600/800 (2R)   X X X 1 X X X X 1 X X X X 1 X
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • An empty table cell indicates that the feature is not currently supported.
  • 1 = Timing is currently preliminary. It will be necessary to recompile designs in future releases.
  • 2 = Applicable to all OPNS for Agilex™ 5 E-Series Device Group B, execept: A5EC065BB23AEXSR0, A5EC065BB32AEXSR0, A5ED065BB23AEXSR0 and A5ED065BB32AEXSR0.

Note: Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com.
Table 9.   Agilex™ 5 E-Series Device Group B Fabric EMIF IP Feature Support Summary 2
Protocol Category Sub-Category Supported? S C T H
DDR4 Interface Width 16, 16+ECC X X X X X
32, 32+ECC X X X X X
Controller Hard controller X X X X X
3DS 3DS          
Design Example   X X X X X
DBI Read DBI X X X X X
Write DBI X X X X X
DM DM pins X X X X X
Preamble Read preamble settings          
Write preamble settings          
Mainband access mode Fabric Direct - User Clock Asynchronous to PHY X X X X X
Fabric Direct - User Clock Synchronous to PHY X X X X X
ECC Out-of-band ECC X X X X X
Debug EMIF Toolkit X X X X X
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX X X      
ModelSim SE X X      
Xcelium X X      
Aldec          
LPDDR4 Interface Width 1ch x32 X X X X X
1ch x16 X X X X X
2ch x16 X X X X X
4ch x16 X X X X X
Controller Hard controller X X X X X
Design Example   X X X X X
DBI Read DBI          
Write DBI X X X X X
DM DM pins X X X X X
Preamble Read preamble settings          
Write preamble settings          
Postamble Read postamble settings X X X X X
Write postamble settings X X X X X
Mainband access mode Fabric Direct - User Clock Asynchronous to PHY X X X X X
Fabric Direct - User Clock Synchronous to PHY X X X X X
ECC In-line ECC X X X X X
Debug EMIF toolkit X X X X X
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX X X      
ModelSim SE X X      
Xcelium X X      
Aldec          
LPDDR5 Interface Width 1ch x32 X X X X X
1ch x16 X X X X X
2ch x16 X X X X X
4ch x16 X X X X X
Controller Hard controller X X X X X
Design Example   X X X X X
DBI Read DBI          
Write DBI X X X X X
DM DM pins X X X X X
Preamble Read preamble settings X X X X X
Write preamble settings          
Postamble Read postamble settings X X X X X
Write postamble settings X X X X X
Mainband access mode Fabric Direct - User Clock Asynchronous to PHY X X X X X
Fabric Direct - User Clock Synchronous to PHY X X X X X
ECC In-line ECC X X X X X
WR Link ECC          
RD Link ECC          
Debug EMIF toolkit X X X X X
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX X X      
ModelSim SE X X      
Xcelium X X      
Aldec          
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 1 = VHDL is not supported.
  • 2 = Applicable to all OPNS for Agilex™ 5 E-Series Device Group B, except: A5EC065BB23AEXSR0, A5EC065BB32AEXSR0, A5ED065BB23AEXSR0 and A5ED065BB32AEXSR0.
Table 10.   Agilex™ 5 E-Series Device Group B HPS EMIF IP Feature Support Summary 1
Protocol Category Sub-Category Supported? S C T H
DDR4 Interface Width 16, 16+ECC X   X X X
32, 32+ECC X   X X X
Controller Hard controller X   X X X
3DS 3DS          
Design Example            
DBI Read DBI X   X X X
Write DBI X   X X X
DM DM pins X   X X X
Preamble Read preamble settings          
Write preamble settings          
Mainband access mode Direct path to HPS X   X X X
ECC Out-of-band ECC X   X X X
Debug EMIF Toolkit          
Simulation Abstract PHY          
Simulators VCS          
VCS-MX          
ModelSim SE          
Xcelium          
Aldec          
LPDDR4 Interface Width 1ch x32 X   X X X
1ch x16 X   X X X
2ch x16 X   X X X
4ch x16 X   X X X
Controller Hard controller X   X X X
Design Example            
DBI Read DBI          
Write DBI X   X X X
DM DM pins X   X X X
Preamble Read preamble settings          
Write preamble settings          
Postamble Read postamble settings X   X X X
Write postamble settings X   X X X
Mainband access mode Direct path to HPS X   X X X
ECC In-line ECC X   X X X
Debug EMIF toolkit          
Simulation Abstract PHY          
Simulators VCS          
VCS-MX          
ModelSim SE          
Xcelium          
Aldec          
LPDDR5 Interface Width 1ch x32 X   X X X
1ch x16 X   X X X
2ch x16 X   X X X
4ch x16 X   X X X
Controller Hard controller X   X X X
Design Example            
DBI Read DBI          
Write DBI X   X X X
DM DM pins X   X X X
Preamble Read preamble settings X   X X X
Write preamble settings          
Postamble Read postamble settings X   X X X
Write postamble settings X   X X X
Mainband access mode Direct path to HPS X   X X X
ECC In-line ECC X   X X X
WR Link ECC          
RD Link ECC          
Debug EMIF toolkit          
Simulation Abstract PHY          
Simulators VCS          
VCS-MX          
ModelSim SE          
Xcelium          
Aldec          
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 1 = Applicable to all OPNS for Agilex 5 E-Series Device Group B except: A5ED065BB23AEXSR0 and A5ED065BB32AEXSR0.
Table 11.   Agilex™ 5 D-Series Device Fabric EMIF/HPS EMIF IP Speed Support Summary
      Max Rate (Mbps/MHz)   -1V -2V -3V
Protocol Category Subcategory -1V -2V -3V Support Detail S C T H S C T H S C T H
DDR4 Memory Format Fabric EMIF - Component/DIMM 3200/1600 (1R) 3200/1600 (1R) 2667/1333 (1R)   X X X 1   X X X 1   X X X 1  
3200/1600 (2R) 3200/1600 (2R) 2667/1333 (2R)   X X X 1   X X X 1   X X X 1  
HPS EMIF - Component 2667/1333 (1R) 2667/1333 (1R) 2133/1066 (1R)   X X X 1   X X X 1   X X X 1  
2667/1333 (2R) 2667/1333 (2R) 2133/1066 (2R)   X X X 1   X X X 1   X X X 1  
DDR5 Memory Format Both Fabric and HPS EMIF - Component/DIMM 4000/2000 (1R) 4000/2000 (1R) 3200/1600 (1R)   X X X 1   X X X 1   X X X 1  
4000/2000 (2R) 4000/2000 (2R) 3200/1600 (2R)   X X X 1   X X X 1   X X X 1  
LPDDR4 Memory Format Both Fabric and HPS EMIF - Component 4266/2133 (1R) 4266/2133 (1R) 3733/1866 (1R)   X X X 1   X X X 1   X X X 1  
4266/2133 (2R) 4266/2133 (2R) 3733/1866 (2R)   X X X 1   X X X 1   X X X 1  
LPDDR5 Memory Format Both Fabric and HPS EMIF - Component 4266/2133 (1R) 4266/2133 (1R) 3733/1866 (1R)   X X X 1   X X X 1   X X X 1  
4266/2133 (2R) 4266/2133 (2R) 3733/1866 (2R)   X X X 1   X X X 1   X X X 1  
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • An empty table cell indicates that the feature is not currently supported.
  • 1 = Timing is currently preliminary. It will be necessary to recompile designs in future releases.

Note: Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com.
Table 12.   Agilex™ 5 D-Series Fabric EMIF IP Feature Support Summary
Protocol Category Sub-Category Supported? S C T H
DDR4 Interface Width 16, 16+ECC X X X X  
32, 32+ECC X X X X  
SODIMM, UDIMM 2 X X X X  
RDIMM 2 X X X X  
Controller Hard controller X X X X  
3DS 3DS          
Design Example   X X X X  
DBI Read DBI X X X X  
Write DBI X X X X  
DM DM pins X X X X  
Preamble Read preamble settings X X X X  
Write preamble settings X X X X  
Mainband access mode Fabric Direct - User Clock Asynchronous to PHY X X X X  
Fabric Direct - User Clock Synchronous to PHY X X X X  
ECC Out-of-band ECC X X X X  
Debug EMIF Toolkit X X X X  
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX X X      
ModelSim SE X X      
Xcelium X X      
Aldec          
DDR5 Interface Width 16, 16+ECC X X X X  
32, 32+ECC X X X X  
SODIMM, UDIMM 2 X X X X  
RDIMM 2 X X X X  
Controller Hard controller X X X X  
Design Example   X X X X  
DM DM pins X X X X  
Preamble Read preamble settings X X X X  
Write preamble settings X X X X  
Postamble Read postamble settings X X X X  
Write postamble settings X X X X  
Mainband access mode Fabric Direct - User Clock Asynchronous to PHY X X X X  
Fabric Direct - User Clock Synchronous to PHY X X X X  
ECC Out-of-band ECC X X X X  
Debug EMIF Toolkit X X X X  
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX X X      
Modelsim SE X X      
Xcelium X X      
Aldec          
LPDDR4 Interface Width 1ch x32 X X X X  
1ch x16 X X X X  
2ch x16 X X X X  
4ch x16 X X X X  
Controller Hard controller X X X X  
Design Example   X X X X  
DBI Read DBI X X X X  
Write DBI X X X X  
DM DM pins X X X X  
Preamble Read preamble settings X X X X  
Write preamble settings          
Postamble Read postamble settings X X X X  
Write postamble settings X X X X  
Mainband access mode Fabric Direct - User Clock Asynchronous to PHY X X X X  
Fabric Direct - User Clock Synchronous to PHY X X X X  
ECC In-line ECC X X X X  
Debug EMIF toolkit X X X X  
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX X X X    
ModelSim SE X X X    
Xcelium X X X    
Aldec          
LPDDR5 Interface Width 1ch x32 X X X X  
1ch x16 X X X X  
2ch x16 X X X X  
Controller Hard controller X X X X  
Design Example   X X X X  
DBI Read DBI X X X X  
Write DBI X X X X  
DM DM pins X X X X  
Preamble Read preamble settings X X X X  
Write preamble settings          
Postamble Read postamble settings X X X X  
Write postamble settings X X X X  
Mainband access mode Fabric Direct - User Clock Asynchronous to PHY X X X X  
Fabric Direct - User Clock Synchronous to PHY X X X X  
ECC In-line ECC X X X X  
WR Link ECC X X X X  
RD Link ECC X X X X  
Debug EMIF toolkit X X X X  
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX X X      
ModelSim SE X X      
Xcelium X X      
Aldec          
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 1 = VHDL is not supported.
  • 2 = Supported only in Fabric Direct - User Clock Synchronous to PHY access mode.
Table 13.   Agilex™ 5 D-Series HPS EMIF IP Feature Support Summary
Protocol Category Sub-Category Supported? S C T H
DDR4 Interface Width 16, 16+ECC X   X X  
32, 32+ECC X   X X  
Controller Hard controller X   X X  
3DS 3DS          
Design Example            
DBI Read DBI X   X X  
Write DBI X   X X  
DM DM pins X   X X  
Preamble Read preamble settings X   X X  
Write preamble settings X   X X  
Mainband access mode Direct path to HPS X   X X  
ECC Out-of-band ECC X   X X  
Debug EMIF Toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX          
ModelSim SE          
Xcelium          
Aldec          
DDR5 Interface Width 16, 16+ECC X   X X  
32, 32+ECC X   X X  
Controller Hard controller X   X X  
Design Example            
DM DM pins X   X X  
Preamble Read preamble settings X   X X  
Write preamble settings X   X X  
Postamble Read postamble settings X   X X  
Write postamble settings X   X X  
Mainband access mode Hard path to HPS X   X X  
ECC Out-of-band ECC X   X X  
Debug EMIF Toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX          
Modelsim SE          
Xcelium          
Aldec          
LPDDR4 Interface Width 1ch x32 X   X X  
1ch x16 X   X X  
2ch x16 X   X X  
4ch x16 X   X X  
Controller Hard controller X   X X  
Design Example            
DBI Read DBI X   X X  
Write DBI X   X X  
DM DM pins X   X X  
Preamble Read preamble settings X   X X  
Write preamble settings          
Postamble Read postamble settings X   X X  
Write postamble settings X   X X  
Mainband access mode Hard path to HPS X   X X  
ECC In-line ECC X   X X  
Debug EMIF toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX          
ModelSim SE          
Xcelium          
Aldec          
LPDDR5 Interface Width 1ch x32 X   X X  
1ch x16 X   X X  
2ch x16 X   X X  
Controller Hard controller X   X X  
Design Example            
DBI Read DBI X   X X  
Write DBI X   X X  
DM DM pins X   X X  
Preamble Read preamble settings X   X X  
Write preamble settings          
Postamble Read postamble settings X   X X  
Write postamble settings X   X X  
Mainband access mode Hard path to HPS X   X X  
ECC In-line ECC X   X X  
WR Link ECC X   X X  
RD Link ECC X   X X  
Debug EMIF toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX          
ModelSim SE          
Xcelium          
Aldec          
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 1 = VHDL is not supported.
Level Two Title