F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide

ID 816968
Date 4/01/2024
Public

2.5. Compilation

Follow the procedure in the Compiling and Configuring the Design Example in Hardware section to compile and configure the design example in the selected hardware.

You can estimate resource utilization and Fmax using the compilation of the project inside the hardware_test_design folder.. You can compile your design using the Start Compilation command on the Processing menu in the Quartus® Prime Pro Edition software. A successful compilation generates the compilation report summary.

For more information, refer to the Quartus® Prime Pro Edition User Guide: Design Compilation.