F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

ID 815243
Date 4/01/2024
Public

1.7. Testing the Design Example in Hardware

After you compile the F-Tile Low Latency 100G Ethernet Intel® FPGA IP design example and configure it on your Agilex™ 7 device, you can use the System Console to program the IP.

To turn on the System Console and test the hardware design example, follow these steps:

  1. In the Quartus® Prime Pro Edition software, select Tools > System Debugging Tools > System Console to launch the system console.
  2. In the Tcl Console pane, type cd hwtest to change directory to /hardware_test_design/hwtest.
  3. Type source main.tcl to open a connection to the JTAG master.
Follow the test procedure in the Hardware Testing section of the design example and observe the test results in the System Console.