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1.1. Directory Structure
1.2. Generating the Design Example
1.3. Command Line IP Generation Flow
1.4. Generating Tile Files
1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Design Example in Hardware
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1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench
Compile and simulate the design by running a simulation script from the command prompt.
Before you begin, you must complete the Support-Logic generation to generate the tile files required for simulation.
- At the command prompt, change the testbench simulating working directory by running the following command:
cd <design_example_dir>/ex_100g_f/sim
- Run the IP setup simulation.
ip-setup-simulation -quartus-project=../../compilation_test_design/alt_e100_f.qpf
- At the command prompt, change the working directory to <design_example_dir>/example_testbench.
- Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator.
Table 3. Instructions to Simulate the Testbench Simulator Command Siemens* EDA QuestaSim* vsim -do run_vsim.do. Synopsys* VCS* sh run_vcs.sh Synopsys* VCS* MX sh run_vcsmx.sh. Cadence* Xcelium* sh run_xcelium.sh Aldec* Riviera-PRO* vsim -do run_riviera.do
A successful simulation ends with the following message:
Simulation Passed.or
Testbench complete.After successful completion, you can analyze the results.