F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

ID 815243
Date 4/01/2024
Public

1.4. Generating Tile Files

The Support-Logic generation is a pre-synthesis step used to generate tile-related files required for simulation and hardware design. The tile generation is required for all F-Tile-based design simulations. You must complete this step before the simulation.
  1. At the command prompt, navigate to the compilation_test_design folder in your example design as follows:
    cd <your_design_path>/compilation_test_design
  2. Run the following command:
    quartus_tlg alt_e100_f