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1.1. Directory Structure
1.2. Generating the Design Example
1.3. Command Line IP Generation Flow
1.4. Generating Tile Files
1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Design Example in Hardware
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1.1. Directory Structure
Figure 2. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Directory Structure
- The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench.
- The compilation-only design example is located in <design_example_dir>/compilation_test_design.
- The hardware configuration and test files (the hardware design example) are located in <design_example_dir>/hardware_test_design.
File Names |
Description |
---|---|
alt_e100_f.qpf | Quartus® Prime project file. |
alt_e100_f.qsf | Quartus® Prime project settings file. |
alt_e100_f.sdc | Synopsys* Design Constraints file. You can copy and modify this file for your own F-Tile Low Latency 100G Ethernet Intel® FPGA IP design. |
alt_e100_f.v | Top-level Verilog HDL design example file. |
alt_e100_f_clock.sdc | Synopsys* Design Constraints file for clocks. |
common/ | Hardware design example support files. |
hwtest/main.tcl | Main file for accessing System Console. |