F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

ID 815243
Date 4/01/2024
Public

1.1. Directory Structure

Figure 2.  F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Directory Structure
  • The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench.
  • The compilation-only design example is located in <design_example_dir>/compilation_test_design.
  • The hardware configuration and test files (the hardware design example) are located in <design_example_dir>/hardware_test_design.
Table 1.  Directory and File Descriptions

File Names

Description

alt_e100_f.qpf Quartus® Prime project file.
alt_e100_f.qsf Quartus® Prime project settings file.
alt_e100_f.sdc Synopsys* Design Constraints file. You can copy and modify this file for your own F-Tile Low Latency 100G Ethernet Intel® FPGA IP design.
alt_e100_f.v Top-level Verilog HDL design example file.
alt_e100_f_clock.sdc Synopsys* Design Constraints file for clocks.
common/ Hardware design example support files.
hwtest/main.tcl

Main file for accessing System Console.