F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

ID 815243
Date 4/01/2024
Public

1.3. Command Line IP Generation Flow

  1. Run the following command:
    qsys-edit --new-component-type=alt_e100_f --family=Agilex7 --
    part=<part_name> --new-quartus-project=<project_name>

    For example:

    qsys-edit --new-component-type=alt_e100_f --family="Agilex7" --part=AGIB027R31B1E1V alt_e100_f.ip &
  2. In the pop-up GUI, select New Quartus Project option to create new project (.qpf) with alt_e100_f.ip included.
  3. Select Create.
Figure 5.  F-Tile Low Latency 100G Ethernet Intel® FPGA IP GUI After Command Line Instructions