GTS CPRI PHY IP Design Example User Guide

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ID 814583
Date 4/07/2025
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. GTS CPRI PHY Altera® FPGA IP Design Example User Guide Archives 4. Document History for GTS CPRI PHY Altera® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench
2. Design Example Description x
2.1. GTS CPRI PHY IP Design Example Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL 2.2.8. Reset Sequencer
1. Quick Start Guide
2. Design Example Description
3. GTS CPRI PHY Altera® FPGA IP Design Example User Guide Archives
4. Document History for GTS CPRI PHY Altera® FPGA IP Design Example User Guide

1.3. Directory Structure

The GTS CPRI PHY IP design example file directories contain the following generated files for the design example:
Figure 2. Directory Structure of the Generated Static Reconfiguration Design Example For dynamic reconfiguraiton design examples, all ex_<datarate>G prefixes are cpriphy_mr
Table 1.  Testbench File DescriptionsFiles in the <design_example_dir>/example_testbench/ directory

File Names

Description

Testbench and Simulation Files

basic_avl_tb_top.sv Top-level testbench file. The testbench instantiates the hardware design example module and runs Verilog HDL tasks to generate and accept packets.
intel_cpriphy_gts_wrapper.sv DUT wrapper that instantiates DUT and other testbench components.
intel_cpriphy_gts_hw.sv Hardware design example module that instantiates DUT and other testbench components.

Testbench Scripts1

run_vsim.do The Siemens* EDA QuestaSim* , or Questa* Intel® FPGA Edition script to run the testbench.
run_vcsmx.sh The Synopsys* VCS* MX script (combined Verilog HDL and SystemVerilog with VHDL) to run the testbench.
run_xcelium.sh The Cadence Xcelium* script to run the testbench.
Table 2.   Hardware Design Example File DescriptionsFiles in the <design_example_dir>/hardware_test_design directory.
File Names Descriptions
intel_cpriphy_gts_hw.qpf Quartus® Prime project file.
intel_cpriphy_gts_hw.qsf Quartus® Prime project settings file.
intel_cpriphy_gts_hw.sdc Synopsys Design Constraints files. You can copy and modify these files for your own Agilex™ 5 device.
intel_cpriphy_gts_hw.v Top-level Verilog HDL design example file.
intel_cpriphy_gts_wrapper.sv DUT wrapper that instantiates DUT and other testbench components.
/hwtest_sl/main_script.tcl Main file for accessing System Console.
1 Ignore any other simulator script in the <design_example_dir>/example_testbench/ folder.
Level Two Title