Visible to Intel only — GUID: hru1700127209594
Ixiasoft
Visible to Intel only — GUID: hru1700127209594
Ixiasoft
4.7. Compiling the GTS JESD204C IP Design
Refer to the Designing with the GTS JESD204C Intel® FPGA IP before compiling the GTS JESD204C IP core design.
To compile your design, click Start Compilation on the Processing menu in the Quartus® Prime software. You can use the generated .ip or .qip file to include relevant files into your project.