Visible to Intel only — GUID: qsz1553277491755
Ixiasoft
Visible to Intel only — GUID: qsz1553277491755
Ixiasoft
3.2.5.1. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines
Skew delay includes the following elements:
- The delay due to the differences in board traces lengths on the PCB
- The capacitance loading of the flash device
Use the following equations to determine the skew between AS_CLK and AS_DATA:
- Skew(AS_CLK – AS_DATA) > –AS_CLK/2 + Tdo(max) + Tsu
- Skew(AS_CLK – AS_DATA) < AS_CLK/2 + Tdo(min) – Tho
Hence, the allowable range for skew between AS_CLK and AS_DATA is as follows:
–AS_CLK/2 + Tdo(max) + Tsu < Skew(AS_CLK – AS_DATA) < AS_CLK/2 + Tdo(min) – Tho
- Tsu = Data setup time required by the quad SPI flash. Refer to your quad SPI flash datasheet.
- Tho = Data hold time required by the quad SPI flash. Refer to your quad SPI flash datasheet.
- Tdo = AS_DATA[3:0] output delay. Refer to the AS configuration timing specifications in the Agilex™ 5 Device Data Sheet .
- AS_CLK = AS_CLK clock period.
Example to Determine the Skew for 1 GB Quad SPI Flash Devices
Tsu = 1.75 ns
Tho = 2.0 ns
Tdo(max) = 0.6 ns
Tdo(min) = –0.6 ns
AS_CLK = 10 ns (100 MHz)
- Skew(AS_CLK – AS_DATA) > –AS_CLK/2 + Tdo(max) + Tsu
Skew(AS_CLK – AS_DATA) > –10/2 + 0.6 + 1.75
Skew(AS_CLK – AS_DATA) > –2.65 ns
- Skew(AS_CLK – AS_DATA) < AS_CLK/2 + Tdo(min) – Tho
Skew(AS_CLK – AS_DATA) < 10/2 – 0.6 – 2.0
Skew(AS_CLK – AS_DATA) < 2.4 ns
The allowable range for skew between AS_CLK and AS_DATA is –2.65 ns < Skew(AS_CLK – AS_DATA) < 2.4 ns