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1. Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 Configuration Details
3. Agilex™ 5 Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Agilex™ 5 Configuration Features
7. Agilex™ 5 Debugging Guide
8. Document Revision History for the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Agilex™ 5 Configuration Timing Diagram
2.2. Configuration Flow Diagram
2.3. Device Response to Configuration and Reset Events
2.4. Additional Clock Requirements for HPS and GTS Transceivers
2.5. Agilex™ 5 Configuration Pins
2.6. Configuration Clocks
2.7. Agilex™ 5 Configuration Time Estimation
2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II Intel® FPGA IP (PFL II)
3.1.7.1. Functional Description
3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration
3.1.7.3. Generating the Parallel Flash Loader II Intel® FPGA IP
3.1.7.4. Constraining the Parallel Flash Loader II Intel® FPGA IP
3.1.7.5. Using the Parallel Flash Loader II Intel® FPGA IP
3.1.7.6. Supported Flash Memory Devices
3.1.7.3.1. Controlling Avalon-ST Configuration with Parallel Flash Loader II Intel® FPGA IP
3.1.7.3.2. Mapping Parallel Flash Loader II Intel® FPGA IP and Flash Address
3.1.7.3.3. Creating a Single Parallel Flash Loader II Intel® FPGA IP for Programming and Configuration
3.1.7.3.4. Creating Separate Parallel Flash Loader II Intel® FPGA IP Functions
3.1.7.4.1. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for using CFI Flash
3.1.7.4.4. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Input Pins
3.1.7.4.5. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Skew Tolerance Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Agilex™ 5 Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. Configuration File Format Differences
7.5. Understanding SEUs
7.6. Reading the Unique 64-Bit CHIP ID
7.7. Understanding and Troubleshooting Configuration Pin Behavior
7.8. Configuration Debugger Tool
7.9. CRAM Integrity Check Feature
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3.1.7.5.4. Defining New CFI Flash Memory Device
The Parallel Flash Loader II Intel® FPGA IP (PFL II) supports Intel® - and AMD-compatible flash memory devices. In addition to the supported flash memory devices, you can define the new Intel® - or AMD-compatible CFI flash memory device in the PFL II-supported flash database using the Define New CFI Flash Device function.
To add a new CFI flash memory device to the database or update a CFI flash memory in the database, follow these steps:
- In the Programmer window, on the Edit menu, select Define New CFI Flash Device. The following table lists the three functions available in the Define CFI Flash Device window.
Table 31. Functions of the Define CFI Flash Device Feature Function Description New Add a new Intel® - or AMD-compatible CFI flash memory device into the PFL II-supported flash database. Edit Edit the parameters of the newly added Intel® - or AMD-compatible CFI flash memory device in the PFL II-supported flash database. Remove Remove the newly added Intel® - or AMD-compatible CFI flash memory device from the PFL II-supported flash database. - To add a new CFI flash memory device or edit the parameters of the newly added CFI flash memory device, select New or Edit. The New CFI Flash Device dialog box appears.
- In the New CFI Flash Device dialog box, specify or update the parameters of the new flash memory device. You can obtain the values for these parameters from the data sheet of the flash memory device manufacturer.
Figure 39. Using the Programmer Edit Menu to Define a New Flash Device
Table 32. Parameter Settings for New CFI Flash Device Parameter Description CFI flash device name Define the CFI flash name CFI flash device ID Specify the CFI flash identifier code CFI flash manufacturer ID Specify the CFI flash manufacturer identification number CFI flash extended device ID Specify the CFI flash extended device identifier, only applicable for AMD-compatible CFI flash memory device Flash device is Intel® compatible Turn on the option if the CFI flash is Intel® compatible Typical word programming time Typical word programming time value in µs unit Maximum word programming time Maximum word programming time value in µs unit Typical buffer programming time Typical buffer programming time value in µs unit Maximum buffer programming time Maximum buffer programming time value in µs unit Note: You must specify either the word programming time parameters, buffer programming time parameters, or both. Do not leave both programming time parameters with the default value of zero. - Click OK to save the parameter settings.
- After you add, update, or remove the new CFI flash memory device, click OK.
The Windows registry stores user flash information. Consequently, you must have system administrator privileges to store the parameters in the Define New CFI Flash Device window in the Quartus® Prime Pro Edition Programmer.