Hard Processor System Component Reference Manual: Agilex™ 5 SoCs
ID
813752
Date
4/10/2025
Public
Visible to Intel only — GUID: khb1686332905053
Ixiasoft
1. Introduction to the Agilex™ 5 Hard Processor System Component
2. Configuring the Agilex™ 5 Hard Processor System Component
3. Simulating the Agilex™ 5 HPS Component
4. Simulating the Agilex™ 5 HPS bridges (H2F, LWH2F, and F2SDRAM)
5. Design Guidelines
6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs
2.1. Parameterizing the HPS Component
2.2. HPS-FPGA Interfaces
2.3. SDRAM
2.4. HPS Clocks, Reset, Power
2.5. I/O Delays
2.6. Pin Mux and Peripherals
2.7. Generating and Compiling the HPS Component
2.8. Using the Address Span Extender Component
2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2.1.1. Enable MPU Standby and Event Signals
2.2.1.2. Enable General Purpose Signals
2.2.1.3. Enable Debug APB* Interface
2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events
2.2.1.5. Enable SWJ-DP JTAG Interface
2.2.1.6. Enable FPGA Cross Trigger Interface
2.2.1.7. Enable AMBA* Trace Bus (ATB)
2.3.1. Configurations for HPS IP
2.3.2. Configurations for HPS EMIF IP
2.3.3. Graphical Connections of HPS to HPS-EMIF
2.3.4. Configuration when using ECC
2.3.5. Configuration of HPS EMIF Calibration Settings
2.3.6. Supported Memory Protocols Among Device Families
2.3.7. IO96 Bank and Lane Usage for HPS EMIF
2.3.8. Quartus Report of I/O Bank Usage
2.3.9. Debugging with the External Memory Interface Debug Toolkit
Visible to Intel only — GUID: khb1686332905053
Ixiasoft
2.1. Parameterizing the HPS Component
- Open the Quartus® Prime software.
Figure 1. Quartus® Prime Starting Screen
- Open Platform Designer by selecting Tools > Platform Designer .
Figure 2. Selecting Platform Designer in Quartus® Prime GUI
- Select an existing Quartus® Prime project and Platform Designer system or create new files. Ensure that Agilex™ 5 device is selected in the Device Family dropdown, and an appropriate device is selected in the Device Part dropdown.
- In the IP Catalog tab, under Library, select Processors and Peripherals > Hard Processor Systems > Hard Processor System Agilex™ 5 FPGA IP.
Figure 3. Platform Designer IP Catalog