Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 7/08/2024
Public
Document Table of Contents

3.5. Analog Parameter Settings

Table 13.  Analog Parameter Settings
Parameter Range Default Settings Description
Analog TX
Spread Spectrum
  • ENABLE
  • DISABLE
DISABLE Specifies if the TX PLL reference clock is spread spectrum.
Enable TX P&N Invert
  • ENABLE
  • DISABLE
DISABLE Polarity Inversion.
TX EQ Post Tap 1, 1.0 step size 019 5 Post tap 1 coefficient, 1.0 step size.
TX EQ Main Tap 1, 1.0 step size 055 52 Main tap coefficient, 1.0 step size.
TX EQ Pre Tap 1, 1.0 step size 015 0 Pre tap 1 coefficient, 1.0 step size.
TX EQ Pre Tap 2, 1.0 step size 07 0 Pre tap 2 coefficient, 1.0 step size.
Analog RX
RX Adaptation mode
  • auto
  • manual
auto Specifiesthe type of RX adaptation.

FLUX_ADAPTATION—Firmware based auto adapatation

MANUAL_ADAPTATION—Firmware based adaptation is disabled and RX analog parameters such as vga_gain, hf_boost, and dfe_tap_1 are used to tune the RX links.

Enable RX P&N Invert
  • ENABLE
  • DISABLE
DISABLE Inverts RX serial input P and N.
RX External Coupling Mode
  • AC
  • DC
AC Specifies the decoupling cap on board.
Selects value of RX termination mode
  • GROUNDED
  • DIFFERENTIAL
GROUNDED Specifies how the RX is terminated.
Selects value of RX onchip termination
  • R_1 (85 ohms)
  • R_2 (100 ohms)
R_2 (100 ohms) Enable RX on-chip termination
Note: The default values apply to 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver variant only.