Visible to Intel only — GUID: owl1717992079154
Ixiasoft
1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
11. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
A. Ethernet Frame Format
B. Simulation Parameters
4.1.1. MAC Architecture
4.1.2. MAC Interfaces
4.1.3. MAC Transmit Datapath
4.1.4. MAC Receive Datapath
4.1.5. MAC Transmit and Receive Latencies
4.1.6. FIFO Buffer Thresholds
4.1.7. Congestion and Flow Control
4.1.8. Magic Packets
4.1.9. MAC Local Loopback
4.1.10. MAC Reset
4.1.11. PHY Management (MDIO)
4.1.12. Connecting MAC to External PHYs
6.1.1. 10/100/1000 Ethernet MAC Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals
6.1.5. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.6. 1000BASE-X/SGMII PCS Signals
6.1.7. 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.1.1. Clock and Reset Signals
6.1.1.2. Clock Enabler Signals
6.1.1.3. MAC Control Interface Signals
6.1.1.4. MAC Status Signals
6.1.1.5. MAC Receive Interface Signals
6.1.1.6. MAC Transmit Interface Signals
6.1.1.7. Pause and Magic Packet Signals
6.1.1.8. MII/GMII/RGMII Signals
6.1.1.9. PHY Management Signals
Visible to Intel only — GUID: owl1717992079154
Ixiasoft
3.5. Analog Parameter Settings
Parameter | Range | Default Settings | Description |
---|---|---|---|
Analog TX | |||
Spread Spectrum |
|
DISABLE | Specifies if the TX PLL reference clock is spread spectrum. |
Enable TX P&N Invert |
|
DISABLE | Polarity Inversion. |
TX EQ Post Tap 1, 1.0 step size | 0–19 | 5 | Post tap 1 coefficient, 1.0 step size. |
TX EQ Main Tap 1, 1.0 step size | 0–55 | 52 | Main tap coefficient, 1.0 step size. |
TX EQ Pre Tap 1, 1.0 step size | 0–15 | 0 | Pre tap 1 coefficient, 1.0 step size. |
TX EQ Pre Tap 2, 1.0 step size | 0–7 | 0 | Pre tap 2 coefficient, 1.0 step size. |
Analog RX | |||
RX Adaptation mode |
|
auto | Specifiesthe type of RX adaptation. FLUX_ADAPTATION—Firmware based auto adapatation MANUAL_ADAPTATION—Firmware based adaptation is disabled and RX analog parameters such as vga_gain, hf_boost, and dfe_tap_1 are used to tune the RX links. |
Enable RX P&N Invert |
|
DISABLE | Inverts RX serial input P and N. |
RX External Coupling Mode |
|
AC | Specifies the decoupling cap on board. |
Selects value of RX termination mode |
|
GROUNDED | Specifies how the RX is terminated. |
Selects value of RX onchip termination |
|
R_2 (100 ohms) | Enable RX on-chip termination |
Note: The default values apply to 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver variant only.