Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813665
Date 7/08/2024
Public
Document Table of Contents

1.3.1. Procedure

You can compile and simulate the design by running a simulation script from the command prompt.
  1. At the command prompt, change the working directory to <Example Design>\simulation\ed_sim\<Simulator> .
  2. Run the following simulation scripts.
    Simulator Working Directory Command
    VCS* MX <Example Design>/simulation/ed_sim/synopsys/vcsmx

    For 10M/100M/1G and 2.5G design example:

    sh tb_run.sh

    For 1G and 2.5G with IEEE 1588 design example: sh tb_run.sh

    For 10M/100M/1G/2.5G/5G/10G (USXGMII) design example:

    sh altera_tb_run.sh
    QuestaSim* <Example Design>/simulation/ed_sim/mentor

    For 10M/100M/1G and 2.5G design example:

    vsim -c -do tb_run.tcl

    For 1G and 2.5G with IEEE 1588 design example: vsim -c -do tb_run.tcl

    For 10M/100M/1G/2.5G/5G/10G (USXGMII) design example:

    vsim -c -do altera_tb_run.tcl
    Xcelium* <Example Design>/simulation/ed_sim/xcelium

    For 10M/100M/1G and 2.5G design example:

    sh tb_run.sh

    For 10M/100M/1G/2.5G/5G/10G (USXGMII) design example:

    sh altera_tb_run.sh
A successful simulation ends with the following message:
Simulation passed.
After successful completion, you can analyze the results.