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1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
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1.3.1. Procedure
You can compile and simulate the design by running a simulation script from the command prompt.
- At the command prompt, change the working directory to <Example Design>\simulation\ed_sim\<Simulator> .
- Run the following simulation scripts.
Simulator Working Directory Command VCS* MX <Example Design>/simulation/ed_sim/synopsys/vcsmx For 10M/100M/1G and 2.5G design example:
sh tb_run.shFor 1G and 2.5G with IEEE 1588 design example: sh tb_run.sh
For 10M/100M/1G/2.5G/5G/10G (USXGMII) design example:
sh altera_tb_run.shQuestaSim* <Example Design>/simulation/ed_sim/mentor For 10M/100M/1G and 2.5G design example:
vsim -c -do tb_run.tclFor 1G and 2.5G with IEEE 1588 design example: vsim -c -do tb_run.tcl
For 10M/100M/1G/2.5G/5G/10G (USXGMII) design example:
vsim -c -do altera_tb_run.tclXcelium* <Example Design>/simulation/ed_sim/xcelium For 10M/100M/1G and 2.5G design example:
sh tb_run.shFor 10M/100M/1G/2.5G/5G/10G (USXGMII) design example:
sh altera_tb_run.sh
A successful simulation ends with the following message:
Simulation passed.
After successful completion, you can analyze the results.