Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813654
Date 8/16/2024
Public

1.2. Generating the Design Example

Generate the design example from the IP Parameter Editor.
Figure 3. Example Design Tab in the Low Latency 40G Ethernet Intel® FPGA IP Parameter Editor

Follow these steps to generate the design example and testbench:

  1. In the Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Quartus® Prime project. The wizard prompts you to specify a device family and device.
  2. In the IP Catalog, locate and select Low Latency 40G Ethernet Intel® FPGA IP . The New IP Variation window appears.
  3. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  4. Click OK. The parameter editor appears.
  5. On the IP tab, specify the parameters for your IP variation.
  6. On the Example Design tab, under Available Example Designs, select the Single Instance of IP core option.
  7. Under Example Design Files, select the Simulation option to generate the testbench, and select the Synthesis option to generate the compilation-only design examples.
  8. Click the Generate Example Design button. The Select Example Design Directory window appears.
  9. If you want to modify the design example directory path or name from the defaults displayed (intel_eth_e40_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).
  10. Click OK.