SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813649
Date 9/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 SEU Mitigation Overview 2. Agilex™ 5 CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Agilex™ 5 SEU Mitigation Implementation Guides 5. IP and Software References 6. Document Revision History for the SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 SEU Mitigation Overview x
1.1. SEU Mitigation Techniques 1.2. Configuration RAM 1.3. Memory Blocks 1.4. Secure Device Manager ECC and SmartVID 1.5. Triple Modular Redundancy 1.6. Failure Rates
2. Agilex™ 5 CRAM Error Mitigation x
2.1. CRAM Error Detection and Correction 2.2. Error Message Queue 2.3. Scrubbing 2.4. SEU Sensitivity Processing 2.5. Design Hierarchy Sensitivity Classification 2.6. Evaluation of System Response to Upsets 2.7. Retrieving SEU Statistics using Mailbox Command
2.2. Error Message Queue x
2.2.1. SEU_ERROR Pin Behavior 2.2.2. Retrieving the Error Message Queue Contents Through Mailbox Command 2.2.3. Retrieving the Error Message Queue Content Using the HPS SDM Mailbox 2.2.4. Error Message Queue Bit Description
2.3. Scrubbing x
2.3.1. Internal Scrubbing 2.3.2. External Scrubbing
2.4. SEU Sensitivity Processing x
2.4.1. Advanced SEU Detection Intel® FPGA IP
2.4.1. Advanced SEU Detection Intel® FPGA IP x
2.4.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.4.1.2. On-Chip Lookup Sensitivity Processing 2.4.1.3. Off-Chip Lookup Sensitivity Processing 2.4.1.4. Sensitivity Map Header Lookup
2.5. Design Hierarchy Sensitivity Classification x
2.5.1. Hierarchy Tagging
2.6. Evaluation of System Response to Upsets x
2.6.1. Fault Injection Debugger
3. Secure Device Manager ECC and SmartVID Errors Detection x
3.1. SDM ECC Error Message Bits 3.2. SmartVID Error Message Bits 3.3. SDM ECC and SmartVID Errors Signals Behavior
4. Agilex™ 5 SEU Mitigation Implementation Guides x
4.1. Setting the SEU_ERROR Pin 4.2. Setting Up the SEU Mitigation Features 4.3. Performing External Scrubbing 4.4. Assigning Regions for Hierarchy Tagging 4.5. Sensitivity Map Header 4.6. Using the Fault Injection Debugger
4.5. Sensitivity Map Header x
4.5.1. Programming the .smh File into Memory 4.5.2. Looking up the Sensitivity Map Header
4.5.2. Looking up the Sensitivity Map Header x
4.5.2.1. Sensitivity Map Header Revision 4 File Format Reference
4.6. Using the Fault Injection Debugger x
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Predefined Safe Locations 4.6.5. Blowing Fuse Bit to Enable Injecting All Error Types 4.6.6. Injecting Errors to Random Locations 4.6.7. Injecting Errors to Specific Locations 4.6.8. Injecting Double Adjacent Errors 4.6.9. Injecting SDM ECC Errors
4.6.4. Injecting Errors to Predefined Safe Locations x
4.6.4.1. Listing the Predefined Safe Locations: Command-Line Interface 4.6.4.2. Injecting Errors to Predefined Safe Locations: Command-Line Interface 4.6.4.3. Injecting Errors to Predefined Safe Locations: GUI with Tcl Console 4.6.4.4. Injecting Error to Predefined Safe Locations: Mailbox Command
4.6.8. Injecting Double Adjacent Errors x
4.6.8.1. Injecting Double Adjacent Errors: Command-Line Interface 4.6.8.2. Injecting Double Adjacent Errors: GUI with Tcl Console
4.6.9. Injecting SDM ECC Errors x
4.6.9.1. Injecting SDM ECC Errors: Command-Line Interface 4.6.9.2. Injecting SDM ECC Errors: GUI with Tcl Console 4.6.9.3. Injecting SDM ECC Errors: Fault Injection Debugger 4.6.9.4. Injecting SDM ECC Errors: Mailbox Command
5. IP and Software References x
5.1. Advanced SEU Detection Intel® FPGA IP References 5.2. Fault Injection Debugger Software References
5.1. Advanced SEU Detection Intel® FPGA IP References x
5.1.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.1.2. Advanced SEU Detection Intel® FPGA IP Ports
5.2. Fault Injection Debugger Software References x
5.2.1. Fault Injection Debugger GUI Tool 5.2.2. Fault Injection Debugger Command-Line Interface
1. Agilex™ 5 SEU Mitigation Overview
2. Agilex™ 5 CRAM Error Mitigation
3. Secure Device Manager ECC and SmartVID Errors Detection
4. Agilex™ 5 SEU Mitigation Implementation Guides
5. IP and Software References
6. Document Revision History for the SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs

2.7. Retrieving SEU Statistics using Mailbox Command

To retrieve SEU statistics (timing of SEU event) in Agilex™ 5 devices, send the mailbox command with the following syntax: 
READ_SEU_STATS (0x40)

Examples of the READ_SEU_STATS (0x40) Mailbox Command:

To retrieve the SEU statistics via the Configuration Debugger tool, you can send 0x40 as the Command Code and 0x30000 in the Parameter List field.

0x30000 refers to the sector 0x3, which is the same sector as the injected SEU error.

Figure 7.  READ_SEU_STATS (0x40) Mailbox Command in the Configuration Debugger Tool

The SEU statistics are measured in cycles. To obtain the timing of SEU event, use the following equation to convert the number of cycles into milliseconds (ms):

Figure 8. Timing of SEU Event Equation
The internal clock frequency refers to the Configuration Clock Source in the General tab of the Device and Pin Options. Altera recommends that you use external configuration clock source (OSC_CLK_1) for better accuracy.
Configuration Clock Source Internal Clock Frequency
Internal oscillator 160–230 MHz
External configuration clock source (OSC_CLK_1)

200 MHz for low-powered devices.

OPN with core speed 6 and power S/X.

For example, A5Exxxxxxxxxx6Sxx and A5Exxxxxxxxxx6Xxx
250 MHz for other Agilex™ 5 devices.

For example:

The T_seu_cycle is 0x000B991C in hexadecimal and it is equals to 0x760,092 in decimal. To convert 760,092 cycles into milliseconds at a frequency of 200 MHz, the timing of SEU event obtained is as follows:

T_seu_cycle = 760,092 cycles / 200 MHz = 3.80046 ms

Table 6.  SEU Statistics
SEU Statistic Description
T_seu_cycle The time between the start of the most recent SEU detection cycle to the previous cycle.
T_seu_detect The most recent time spent in performing the SEU detection within a SEU cycle.
T_seu_correct

The most recent time spent in performing the SEU correction (internal scrubbing) within a SEU cycle if a correctable error is detected.

0x FFFFFFFF if no correction is done.
T_seu_inject_detect

The most recent duration from the SEU error being injected to the time the SEU is detected.

0x FFFFFFFF if no injection is done.
T_sdm_seu_poll_interval The time between the start of the most recent SDM check cnoc_return_interrupt line (if there is an SEU error) to the previous one. Use T_sdm_seu_poll_interval to measure the SDM SEU error polls interval.
T_sdm_seu_pin_toggle_overhead The time for SDM to toggle the SEU_ERROR pin after SDM detects error when polling the SEU error (check_cnoc_return_interrupt).
  • To obtain SEU Inject to Detect Cycle (best case), inject a safe SEU error by sending this mailbox command: INSERT_SAFE_SEU_ERROR [0x41] with the T=01 option (inject before next detection cycle), followed by sending READ_SEU_STATS [0x40].
  • To obtain SEU Inject to Detect Cycle (worst case), send the INSERT_SAFE_SEU_ERROR [0x41] mailbox command with the T=10 option (inject after next detection/correction cycle).
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