Intel® Simics® Simulator for Intel® FPGAs: User Guide

Download PDF
ID 784383
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Intel® Simics® Simulator and Virtual Platforms 3. Intel® Simics® Simulator for Intel® FPGAs Device Portfolio 4. Installing the Intel® Simics® Simulator for Intel® FPGAs 5. Getting Started with Intel® Simics® Simulator 6. Debugging Target Software 7. Networking with the Simulated Target System 8. Intel® Simics® Scripting 9. Software Debug Examples with Intel® Simics® Simulator 10. Document Revision History for Intel® Simics® Simulator for Intel FPGAs User Guide A. Intel® Simics® Simulator Command Reference
1. About This Document x
1.1. Documentation Conventions for Examples 1.2. Terminology 1.3. List of Acronyms
2. Intel® Simics® Simulator and Virtual Platforms x
2.1. Device Model and Virtual Platforms 2.2. Intel® Simics® Simulator 2.3. Intel® Simics® Simulator Architecture
2.2. Intel® Simics® Simulator x
2.2.1. Intel® Simics® Simulator for Intel FPGAs Capabilities
4. Installing the Intel® Simics® Simulator for Intel® FPGAs x
4.1. Installing the Intel® Simics® Simulator for Intel® FPGAs on Linux* Systems 4.2. Installing the Intel® Simics® Simulator for Intel® FPGAs on Microsoft Windows* Systems 4.3. Installing Ashling* RiscFree* IDE for Intel® FPGAs 4.4. Intel® Simics® Simulator for Intel® FPGAs Support
5. Getting Started with Intel® Simics® Simulator x
5.1. Simulation Set Up 5.2. Starting the Simulation 5.3. Intel® Simics® Simulator Command-Line Interface (CLI) 5.4. Hardware Inspection 5.5. Intel® Simics® Simulator Timing
5.1. Simulation Set Up x
5.1.1. Initializing an Intel® Simics® Project and Deploying a Virtual Platform 5.1.2. Understanding Target Scripts
5.2. Starting the Simulation x
5.2.1. Starting a Simulation from a Command Prompt 5.2.2. Starting a Simulation with Ashling* RiscFree* IDE
5.3. Intel® Simics® Simulator Command-Line Interface (CLI) x
5.3.1. Version of the Intel® Simics® Simulator for Intel FPGAs Software 5.3.2. Simulation Run Control from CLI 5.3.3. Intel® Simics® Simulator Command Scope 5.3.4. Intel® Simics® Simulator CLI Variables and Operations 5.3.5. Intel® Simics® Simulator CLI Command Completion and Command History 5.3.6. Intel® Simics® Command-Line Interface Help 5.3.7. Capture of CLI Session to a File 5.3.8. Intel® Simics® Simulator File Location and Intel® Simics® Search Path
5.4. Hardware Inspection x
5.4.1. Listing Objects in the Target System 5.4.2. Processor (CPU) Inspection 5.4.3. Device Inspection 5.4.4. Memory Mapping and Memory Inspection 5.4.5. Logging
5.4.2. Processor (CPU) Inspection x
5.4.2.1. Listing Processors 5.4.2.2. Inspect Processor Registers
5.4.3. Device Inspection x
5.4.3.1. Retrieve List of Devices 5.4.3.2. Inspecting Device Registers
5.4.4. Memory Mapping and Memory Inspection x
5.4.4.1. Memory Mapping Inspection 5.4.4.2. Memory Inspection
5.4.5. Logging x
5.4.5.1. Breakpoints on CLI Log Messages
5.5. Intel® Simics® Simulator Timing x
5.5.1. CPU Frequency 5.5.2. CPU Cycles and Steps 5.5.3. Events 5.5.4. Enable Real Time
6. Debugging Target Software x
6.1. Intel® Simics® Debugger and Debug Context 6.2. Capturing Serial Console Output 6.3. Breakpoints 6.4. Debugging Target Software with Symbol Files 6.5. Debugging Target Software with Ashling* RiscFree* Debugger 6.6. Capturing CPU Instruction Execution Trace
6.3. Breakpoints x
6.3.1. Memory Breakpoints 6.3.2. Temporal Breakpoints 6.3.3. CPU Control Register Breakpoints 6.3.4. Hardware Access Breakpoints 6.3.5. CPU Register Breakpoints 6.3.6. Tracing Breakpoints 6.3.7. Text Console Activity Breakpoints
6.4. Debugging Target Software with Symbol Files x
6.4.1. Loading Symbol Files in a Simulation
6.5. Debugging Target Software with Ashling* RiscFree* Debugger x
6.5.1. Remote Debugging with RiscFree* IDE
6.5.1. Remote Debugging with RiscFree* IDE x
6.5.1.1. Remote Debugging With Intel® Simics® Simulation and RiscFree* IDE on the Same System 6.5.1.2. Remote Debugging With Intel® Simics® Simulation and RiscFree* IDE on Different Systems 6.5.1.3. Remote Access to the Target System Serial Console
7. Networking with the Simulated Target System x
7.1. Network Simulation and Service Node 7.2. Connectivity Between Host PC and Target System
7.2. Connectivity Between Host PC and Target System x
7.2.1. Port Forwarding 7.2.2. Transferring Files Between Host PC and Target System 7.2.3. Accessing Target System from Host PC Through HTTP 7.2.4. Networking Commands Reference Table
7.2.1. Port Forwarding x
7.2.1.1. Incoming Port Forwarding 7.2.1.2. Outgoing Port Forwarding
7.2.1.1. Incoming Port Forwarding x
7.2.1.1.1. Example of an SSH Connection with Incoming Port Forwarding
7.2.1.2. Outgoing Port Forwarding x
7.2.1.2.1. Example of SSH Connection With Outgoing Port Forwarding 7.2.1.2.2. Example of SSH Connection via NAPT
7.2.2. Transferring Files Between Host PC and Target System x
7.2.2.1. Transferring Files with SCP service 7.2.2.2. Transferring Files with TFTP service
7.2.2.1. Transferring Files with SCP service x
7.2.2.1.1. Transferring Files With SCP Service via Forwarding Ports 7.2.2.1.2. Transferring Files with SCP from Target System to Host PC via NAPT
7.2.2.2. Transferring Files with TFTP service x
7.2.2.2.1. TFTP Using Forwarding Port 7.2.2.2.2. TFTP via NAPT 7.2.2.2.3. TFTP Using TFTP Server in Intel® Simics® Service Node
8. Intel® Simics® Scripting x
8.1. Scripts in CLI
8.1. Scripts in CLI x
8.1.1. Variables 8.1.2. Command Return Values 8.1.3. Control Flow Commands 8.1.4. Local Variables 8.1.5. Integer Conversion 8.1.6. Accessing Configuration Parameters 8.1.7. Error Handling in Scripts 8.1.8. Script Branches
8.1.8. Script Branches x
8.1.8.1. Script Branches Commands 8.1.8.2. Variables in Script Branches 8.1.8.3. Branch Synchronization 8.1.8.4. Canceling Script Branches 8.1.8.5. Script Branches Restrictions
9. Software Debug Examples with Intel® Simics® Simulator x
9.1. Debugging Linux* User-Mode Application
9.1. Debugging Linux* User-Mode Application x
9.1.1. Debugging a Linux Application with GDB 9.1.2. Debugging a Linux Application with RiscFree* IDE
9.1.1. Debugging a Linux Application with GDB x
9.1.1.1. Debugging with GDB Debug from Host PC Using Forwarding Ports 9.1.1.2. Debugging with GDB from Host PC with Intel® Simics® Simulator GDB Server
1. About This Document
2. Intel® Simics® Simulator and Virtual Platforms
3. Intel® Simics® Simulator for Intel® FPGAs Device Portfolio
4. Installing the Intel® Simics® Simulator for Intel® FPGAs
5. Getting Started with Intel® Simics® Simulator
6. Debugging Target Software
7. Networking with the Simulated Target System
8. Intel® Simics® Scripting
9. Software Debug Examples with Intel® Simics® Simulator
10. Document Revision History for Intel® Simics® Simulator for Intel FPGAs User Guide
A. Intel® Simics® Simulator Command Reference

6.3.4. Hardware Access Breakpoints

Intel® Simics® simulator provides the capability to create breakpoints associated with the access of registers in a device. This can be useful to debug target software as you can identify whenever a register or set of registers is accessed. There are several Intel® Simics® simulator commands that you can use for this.

Table 21.  Commands to Create Breakpoints

Command

Description

bp.bank.break Enables breaking the simulation on register bank accesses.
bp.bank.run-until Runs the simulation until the specified register bank access occurs.
bp.bank.trace Enables tracing of register bank accesses. When this is enabled, every time the specified register bank access occurs during simulation, a message is printed.
bp.bank.wait-for Postpones execution of a script branch until the specified register bank access occurs.

These commands allow you to set a breakpoint in a read or write access to a full bank of registers or in single register defined by its name or by its offset. It also allows you to set a breakpoint in accessing a set of registers defined with an address range or when the register gets written to a specific value.

The following capture shows some examples that demonstrate the use of these commands. To exercise these scenarios, the target software must generate read/write accesses to the objects specified in the commands: 
#Intel Simics simulator CLI 

# Exercise 1
simics> bp.bank.break system.board.fpga.soc_inst.hps_subsys.agilex_hps.gpio0.bank.regs -r
Breakpoint 1: Will break on read access on system.board.fpga.soc_inst.hps_subsys.agilex_hps.gpio0.bank.regs
simics> r
running> devs agilex.gpio0.bank.regs
-------------------------------------------------------------------------
Count   Device                      Space                  Range
-------------------------------------------------------------------------
    0   system....gpio0...   system....phys_mem  0x10c03200 - 0x10c032ff
-------------------------------------------------------------------------
[system...agilex_hps.gpio0.bank.regs] Breakpoint 1: system...agilex_hps.gpio0.bank.regs read at 
offset=0xfc size=0x4 value=0x0 ini=system...agilex_hps.core[0]

Exercise 1 sets a breakpoint on a read access to any of the registers under the gpio0 device. This creates a breakpoint with the ID 1. The simulation is run and at this point, it is expected that the target software does a read access to a register under this bank (address 0x10c032fc used in this example). After doing the read access, you can observe that the simulation was stopped as a consequence of the breakpoint trigger. 

#Intel Simics simulator CLI

# Exercise 2

simics> devs system.board.fpga.soc_inst.hps_subsys.agilex_hps.gpio1.bank.regs
-----------------------------------------------------------------
      Device               Space                   Range
-----------------------------------------------------------------
system...bank.regs  system...phys_mem     0x10c03300 – 0x10c033ff
-----------------------------------------------------------------

simics> print-device-regs system.board.fpga.soc_inst.hps_subsys.agilex_hps.gpio1

------------------------------------------------
Offset      Name                Size      Value
------------------------------------------------
0          GPIO_SWPORTA_DR        4         0
4          GPIO_SWPORTA_DDR       4         0
:
116        GPIO_CONFIG_REG1       4       0x1ff0f2
------------------------------------------------

simics> bp.bank.trace system.board.fpga.soc_inst.hps_subsys.agilex_hps.gpio1.bank.regs register = GPIO_CONFIG_REG1
1
simics> bp.bank.run-until system.board.fpga.soc_inst.hps_subsys.agilex_hps.gpio1.bank.regs register=GPIO_CONFIG_REG1 -w value=0xcafe
simics> bp.bank.run-until system.board.fpga.soc_inst.hps_subsys.agilex_hps.gpio1.bank.regs register=GPIO_CONFIG_REG1 -w value=0xcafe
[bp.bank trace] [trace:1] system.board.fpga.soc_inst.hps_subsys.agilex_hps.gpio1.bank.regs read at offset=0x74 size=0x4 value=0x1ff0f2 ini=system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0]
[bp.bank trace] [trace:1] system.board.fpga.soc_inst.hps_subsys.agilex_hps.gpio1.bank.regs write at offset=0x74 size=0x4 value=0xcafe ini=system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0]
simics>
Exercise 2 sets two breakpoints over the GPIO_CONFIG_REG1 register in GPIO1 device (at offset 0x10c03300 in this example):
  • The first one is a trace to detect any read/write operation in the register, this gets an ID of 1.
  • The second breakpoint is set with the run-until command. This breakpoint is configured to trigger on a write operation to the same register with the value 0xcafe.
After this command, the simulation automatically runs in the background and the Intel® Simics® simulator waits for any of the events to occur.

In this example, a read operation to the register is done in the target software followed by the expected write operation. After this, you can see that a couple of messages are printed describing the read and write operations and also the simulation is stopped as a consequence of the last breakpoint.

The command used to set up the breakpoints presented in this section can be called directly over the objects used as argument. For this, the following commands can be used instead:

  1. <object>.regs.bp-break-bank
  2. <object>.regs.bp-run-until-bank
  3. <object>.regs.bp-trace-bank
  4. <object>.regs.bp-wait-for-bank
Level Two Title