External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide

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ID 772632
Date 1/13/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP 4. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Parameterizing the External Memory Interface for HPS IP 2.4. Configuring DQ Pin Swizzling 2.5. Generating the Synthesizable EMIF Design Example 2.6. Generating the EMIF Design Example for Simulation 2.7. Pin Placement for Agilex™ 7 M-Series EMIF IP 2.8. Compiling the Agilex™ 7 M-Series EMIF Design Example 2.9. Using the EMIF Design Example with the Test Engine IP 2.10. Generating the EMIF Design Example with the Performance Monitor
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 7 M-Series EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Timing and I/O Configuration
2.3. Parameterizing the External Memory Interface for HPS IP x
2.3.1. Parameterization Flow 2.3.2. Parametering the EMIF HPS IP 2.3.3. Parameterizing the EMIF IP
2.4. Configuring DQ Pin Swizzling x
2.4.1. Example: DQ Pin Swizzling Within DQS group for x32 DDR4 interface 2.4.2. Example: Byte Swizzling for a x32 DDR4 interface, using a memory device of x8 width 2.4.3. Combining Pin and Byte Swizzling 2.4.4. Example: Swizzling for a x32 + ECC interface 2.4.5. Example: Swizzling for a 2Ch x32 + ECC interface 2.4.6. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation For ModelSim* SE and Siemens* EDA QuestaSim*- Intel FPGA Edition Simulators For VCS Simulator Cycle-Accurate NoC Simulation
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP
4. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide

3.2.1. Running Simulation

To run a simulation, navigate to the simulation directory <example_design_directory>/sim/ed_sim/ and run the simulation script of your choice.

For ModelSim* SE and Siemens* EDA QuestaSim*- Intel FPGA Edition Simulators

Working directory: <example_design_directory>/sim/ed_sim/mentor

  1. Invoke vsim by typing vsim, which launches a window where you can run the following commands.
  2. Change directory to the design example simulator directory (File > Change directory.
  3. Run the following commands on the transcript terminal:
    1. Do: source msim_setup.tcl
    2. ld_debug
    3. run -all
  4. A successful simulation ends with the following message: Simulation stopped due to successful completion!

For VCS Simulator

Working directory: <example_design_directory>/sim/ed_sim/synopsys/vcs

  1. On a single line, type: 
    sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" USER_DEFINED_SIM_OPTIONS=""
  2. A successful simulation ends with the following message: Simulation stopped due to successful completion!

To run a simulation in interactive mode, follow these steps:

Note: If you have already generated a simv executable in noninteractive mode, delete the simv and simv.diadir.
  1. Open the vcs_setup.sh file and add a debug option to the VCS command: vcs -debug_access+r
  2. Compile the design example: sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS="- xlrm\ uniq_prior_final" SKIP_SIM=1
  3. Start the simulation in interactive mode: simv -gui &

Cycle-Accurate NoC Simulation

EMIF IP designs that use the NoC can enable a cycle-accurate NoC simulation model; to do so, follow these steps:

  1. Compile your ED project up to the Plan stage of the Fitter.
  2. The system creates a file called noc_sim_defparams.inc in the qii/ folder.
  3. Modify the noc_sim_defparams.inc file, to add the line `define SIM_TOP_PATH before initial begin, as shown:
    `define SIM_TOP_PATH ed_sim
initial begin
  #1;
  $display("Using NOC accurate model");
  4. Save the noc_sim_defparams.inc file, and then paste a copy into your simulator directory, as follows:
    • For ModelSim* SE and Siemens* EDA QuestaSim*- Intel FPGA Edition Simulators: <example_design_directory>/sim/ed_sim/mentor
    • For VCS: <example_design_directory>/sim/ed_sim/synopsys/vcs.
  5. Open the <example_design_directory>/sim/ed_sim/sim/ed_sim.v file in an editor, navigate to the bottom of the file, and comment the line `include "ed_sim_noc_sim.inc" and add `include "noc_sim_defparams.inc" immediately before the endmodule line, as shown below:
       //`include "ed_sim_noc_sim.inc"
   `include "noc_sim_defparams.inc"
 
endmodule

The next steps depend on which simulator you are using, as follows:

For ModelSim* SE and Siemens* EDA QuestaSim*- Intel FPGA Edition simulators:

  1. In an editor, open the <example_design_directory>/sim/ed_sim/mentor/msim_setup.tcl file.
  2. Find the line set USER_DEFINED_COMPILE_OPTIONS "-O0" and change it to: set USER_DEFINED_COMPILE_OPTIONS "+define+PERFORMANCE_ACC_NOC_SIM_MODEL_AGILEX"
  3. Save the file and then follow the usual instructions to launch the simulation.

For VCS simulator:

  1. In an editor, open the <example_design_directory>/sim/ed_sim/synopsys/vcs/vcs_setup.sh file.
  2. Find the line USER_DEFINED_ELAB_OPTIONS="" and change it to USER_DEFINED_ELAB_OPTIONS="+define+PERFORMANCE_ACC_NOC_SIM_MODEL_AGILEX".
  3. Save the file and then follow the usual instructions to launch the simulation.
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