The FPGA AI Suite consists of several components to help you enable AI on your Altera FPGAs.

The FPGA AI Suite consists of the following components:

• IP

  The FPGA AI Suite IP is an RTL-instantiable IP with AXI interfaces. These interfaces can be instantiated into a generic FPGA system.

  For a list of models supported by the FPGA AI Suite IP, refer to "Supported Models" in the FPGA AI Suite IP Reference Manual

• Compiler (dla_compiler command)
  The FPGA AI Suite compiler is a multipurpose tool that you can use for the following tasks with the FPGA AI Suite:

  • Generate architectures

    Use the compiler to generate an IP parameterization that is optimized for a given machine learning (ML) model or set of models, while attempting to fit the FPGA AI Suite IP block into a given resource footprint.

  • Estimate IP performance

    Use the compiler to get an estimate of the performance of the AI IP block for a given parameterization.

  • Estimate IP FPGA resource consumption

    Use the compiler to get an estimate of the FPGA resources (ALMs, M20k blocks, and DSPs) required for a given IP parameterization.

  • Create an ahead-of-time compiled graph

    Create a compiled version of an ML model that includes the instructions necessary to control the IP on the FPGA. The compiled binary includes both the instructions to control the IP during inference and the model weights. This compiled model is suitable for use by the Example Designs or in a production deployment.

  An OpenVINO™ plugin is distributed with the compiler that allows the PCIe Example Design to access the compiler in a just-in-time fashion.

• IP generation tool

The FPGA AI Suite IP generation tool customizes the FPGA AI Suite IP based on an input architecture file. The generated IP is placed into an IP library that you can import into an FPGA design with Platform Designer, use directly in a pure RTL design, or both.

• Design examples
  The following design examples show how you can use the FPGA AI Suite IP:

  Table 2.   FPGA AI Suite Design Examples

  Design Example	Description
  PCIe-based design example	Demonstrates how OpenVINO™ toolkit and the FPGA AI Suite support the look-aside deep learning acceleration model. This design example targets the Terasic* DE10-Agilex Development Board (DE10-Agilex-B2E2).
  OFS PCIe-attach design example	Demonstrates the OpenVINO™ toolkit and the FPGA AI Suite that target Open FPGA Stack (OFS)-based boards. This design example targets the following Open FPGA Stack (OFS)-based boards: Agilex™ 7 FPGA I-Series Development Kit ES2 (DK-DEV-AGI027RBES) Intel® FPGA SmartNIC N6001-PL Platform (without Ethernet controller)
  Hostless DDR-Free design examples	Demonstrates hostless DDR-free operation of the FPGA AI Suite IP. Graph filters, bias, and FPGA AI Suite IP configurations are stored in internal memory on the FPGA device. This design example targets the Agilex™ 7 FPGA I-Series Development Kit ES2 (DK-DEV-AGI027RBES).
  Hostless JTAG design example	Demonstrates the step-by-step sequence of configuring FPGA AI Suite IP and starting inference by writing into CSRs directly via JTAG. This design example targets the Agilex™ 5 FPGA E-Series 065B Modular Development Kit (MK-A5E065BB32AES1).
  SoC design example	Demonstrates how OpenVINO™ toolkit and the FPGA AI Suite support the CPU-offload deep-learning acceleration model in an embedded system. The design example targets the following development boards: Agilex™ 5 FPGA E-Series 065B Modular Development Kit (MK-A5E065BB32AES1). Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (DK-SI-AGI027FC) Arria® 10 SX SoC FPGA Development Kit (DK-SOC-10AS066S)