F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

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ID 758946
Date 4/03/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide 2. About this IP 3. Getting Started 4. F-Tile Low Latency 50G Ethernet Intel® FPGA IP Parameters 5. Functional Description 6. Reset 7. Interfaces and Signal Descriptions 8. Control, Status, and Statistics Register Descriptions 9. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide
2. About this IP x
2.1. Release Information 2.2. Features 2.3. Device Family Support 2.4. Performance and Resource Utilization
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IPs 3.2. Specifying the IP Parameters and Options 3.3. Simulating the IP 3.4. Generated File Structure 3.5. Integrating Your IP in Your Design 3.6. Compiling the Full Design and Programming the FPGA
3.1. Installing and Licensing Intel® FPGA IPs x
3.1.1. Intel® FPGA IP Evaluation Mode
3.5. Integrating Your IP in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the F-Tile Reference and System PLL Clocks Intel® FPGA IP 3.5.3. Placement Settings for the 50G Ethernet Intel FPGA IP
5. Functional Description x
5.1. F-Tile Low Latency 50G Ethernet Intel® FPGA IP Functional Description 5.2. User Interface to Ethernet Transmission
5.1. F-Tile Low Latency 50G Ethernet Intel® FPGA IP Functional Description x
5.1.1. F-Tile Low Latency 50G Ethernet Intel® FPGA IP TX MAC Datapath 5.1.2. 50 GbE TX PCS 5.1.3. F-Tile Low Latency 50G Ethernet Intel® FPGA IP RX MAC Datapath 5.1.4. Link Fault Signaling Interface 5.1.5. 50 GbE RX PCS 5.1.6. Flow Control
5.1.1. F-Tile Low Latency 50G Ethernet Intel® FPGA IP TX MAC Datapath x
5.1.1.1. Frame Padding 5.1.1.2. Preamble Insertion 5.1.1.3. Inter-Packet Gap Generation and Insertion 5.1.1.4. Frame Check Sequence (CRC32) Insertion
5.1.3. F-Tile Low Latency 50G Ethernet Intel® FPGA IP RX MAC Datapath x
5.1.3.1. IP Preamble Processing 5.1.3.2. IP Malformed Packet Handling 5.1.3.3. Length/Type Field Processing
5.1.3.3. Length/Type Field Processing x
5.1.3.3.1. Length Checking 5.1.3.3.2. RX CRC Checking and Dynamic Forwarding
5.1.6. Flow Control x
5.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 5.1.6.2. XON/XOFF Pause Frames
5.2. User Interface to Ethernet Transmission x
5.2.1. Order of Transmission 5.2.2. Bit Order For TX and RX Datapaths
7. Interfaces and Signal Descriptions x
7.1. TX MAC Interface to User Logic 7.2. RX MAC Interface to User Logic 7.3. Transceivers 7.4. Transceiver Reconfiguration Signals 7.5. Avalon® Memory-Mapped Management Interface 7.6. Miscellaneous Status and Debug Signals 7.7. Flow Control Signals 7.8. Clock Signals 7.9. Reset Signals
8. Control, Status, and Statistics Register Descriptions x
8.1. TX MAC Registers 8.2. RX MAC Registers 8.3. Pause/PFC Flow Control Registers 8.4. Statistics Registers 8.5. Hard IP Registers
8.4. Statistics Registers x
8.4.1. Statistics Registers
1. About the F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile Low Latency 50G Ethernet Intel® FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

3.1. Installing and Licensing Intel® FPGA IPs

The Quartus® Prime Pro Edition software installation includes the Intel® FPGA IP library. This library provides many useful IPs for your production use without the need for an additional license. Some Intel® FPGA IPs require purchase of a separate license for production use. The Intel® FPGA IP Evaluation Mode allows you to evaluate these licensed Intel® FPGA IPs in simulation and hardware, before deciding to purchase a full production IP license. You only need to purchase a full production license for licensed Intel® IPs after you complete hardware testing and are ready to use the IP in production.

The Quartus® Prime software installs IPs in the following locations by default:

Figure 3. IP Installation Path


Table 4.  IP Installation Locations
Location Software Platform
<drive>:\intelFPGA_pro\quartus\ip\altera Quartus® Prime Pro Edition software Windows*
<home directory>:/intelFPGA_pro/quartus/ip/altera Quartus® Prime Pro Edition software Linux*

Section Content
Intel FPGA IP Evaluation Mode

Level Two Title