AN 988: Using the Board-Aware Flow: in the Intel® Quartus® Prime Pro Edition Software

ID 757339
Date 1/09/2023
Public

2.4.5. Step 5: Compile and Verify the Design

Follow these steps to compile the top-level design that includes the pio_led Platform Designer system.
  1. After Platform Designer HDL generation is complete, click Processing > Start Compilation. The Compiler runs for approximately 15 minutes, depending on your system, and generates the SOF programming file following successful compilation.
  2. When full compilation is complete, click Assignments > Pin Planner to verify the following appropriate pin assignments are implemented during compilation:
    Figure 22. Verifying Location Assignments in Pin Planner