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Ixiasoft
2.4.5. Step 5: Compile and Verify the Design
Follow these steps to compile the top-level design that includes the pio_led Platform Designer system.
- After Platform Designer HDL generation is complete, click Processing > Start Compilation. The Compiler runs for approximately 15 minutes, depending on your system, and generates the SOF programming file following successful compilation.
- When full compilation is complete, click Assignments > Pin Planner to verify the following appropriate pin assignments are implemented during compilation:
Figure 22. Verifying Location Assignments in Pin Planner